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downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 1 document no.: pmc-2001304, issue 7 pm3392 s/uni 1x10ge saturn user interface for 10 gigabit ethernet lan phy data sheet proprietary and confidential released issue no. 7: december, 2006
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 2 document no.: pmc-2001304, issue 7 legal information copyright copyright 2006 pmc-sierra, inc. all rights reserved. the information in this document is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, no part of this document may be reproduced or redistributed in any form without the ex press written consent of pmc-sierra, inc. pmc-2001304 (r7). disclaimer none of the information contained in this doc ument constitutes an express or implied warranty by pmc-sierra, inc. as to the sufficiency, fitn ess or suitability for a particular purpose of any such information or the fitness, or suitabilit y for a particular purpose, merchantability, performance, compatibility with other parts or sy stems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in th is document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regard ing the contents or use of the information, including, but not limited to, express and imp lied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including , but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. trademarks s/uni and saturn are registered trademarks of pmc-sierra, inc. crsu-4x2488, pos-phy level 4, and pmc-sierra are trademarks of pmc-sierra, inc. other product and company names mentioned herein may be the tr ademarks of their respective owners. patents the technology discussed in this document may be protected by one or more patent grants.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 3 document no.: pmc-2001304, issue 7 contacting pmc-sierra pmc-sierra 100-2700 production way burnaby, bc canada v5a 4x1 tel: +1 (604) 415-6000 fax: +1 (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 4 document no.: pmc-2001304, issue 7 revision history issue no. issue date details of change 7 december 2006 updated package and ordering information. 6 february 2006 updated ordering information including rohs-compliant device details. 5 october 2002 issue 5 data sheet created. 4 august 2002 issue 4 data sheet created. converted document to new template, modified doc to fix all doc. related prep?s. 3 january 2002 issue 3 data sheet created. 2 october 2001 issue 2 data sheet created. 1 september 2000 preliminary data sheet created.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 5 document no.: pmc-2001304, issue 7 table of contents legal inform ation.............................................................................................................. ............. 2 copyri ght...................................................................................................................... ........... 2 disclaimer ..................................................................................................................... .......... 2 trademarks ..................................................................................................................... ........ 2 patents 2 contacting pmc-sierra.......................................................................................................... ........ 3 revision hi story............................................................................................................... .............. 4 table of content s.............................................................................................................. ............. 5 list of r egisters.............................................................................................................. ............... 8 list of figures ................................................................................................................ .............. 13 list of tables................................................................................................................. ............... 15 1 definitions .................................................................................................................... ......... 17 2 features ....................................................................................................................... ......... 19 2.1 general...................................................................................................................... 19 2.2 10 gigabit et hernet mac .......................................................................................... 19 2.3 statistics .................................................................................................................... 20 2.4 pos-phy level 4 interface ...................................................................................... 20 3 applicat ions................................................................................................................... ........ 21 4 references..................................................................................................................... ....... 22 5 application examples........................................................................................................... . 23 6 block diagram.................................................................................................................. ..... 24 7 description .................................................................................................................... ........ 26 8 pin diag ram .................................................................................................................... ...... 28 9 pin descr iption ................................................................................................................ ...... 31 10 functional de scription ......................................................................................................... . 57 10.1 primary interfaces, li ne side and syst em side........................................................ 57 10.2 receive channel (i ngress) ? line side to system side ........................................... 57 10.3 transmit channel (egress) ? system side to line side........................................... 70 10.4 management statis tics (mstat) ............................................................................... 77 10.5 management data interface...................................................................................... 79 10.6 jtag test access port interface............................................................................... 79 10.7 microprocessor interface........................................................................................... 80 11 normal mode regist er description....................................................................................... 81
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 6 document no.: pmc-2001304, issue 7 12 test features description ................................................................................................... 293 12.1 high impedance state for io................................................................................... 293 12.2 test registers.......................................................................................................... 293 12.3 jtag test port ........................................................................................................ 295 13 operation ...................................................................................................................... ...... 303 13.1 power seque ncing .................................................................................................. 303 13.2 device reset ........................................................................................................... 303 13.3 line-side lvds inte rface ov erview........................................................................ 304 13.4 pos-phy level 4 introduc tion................................................................................ 304 13.5 pos-phy level 4 clocking..................................................................................... 306 13.6 pos-phy level 4 initialization................................................................................ 308 13.7 pl4 bus operation .................................................................................................. 314 13.8 xsbi wrapper line interface .................................................................................. 322 13.9 loopback oper ation................................................................................................ 323 13.10 controlling ethernet frame re ception and transmission ...................................... 324 13.11 ten gigabit ethernet in terframeg ap support ........................................................ 325 13.12 ten gigabit ethernet preamble support ................................................................. 327 13.13 ten gigabit ethernet mac transmit padding and crc generation ...................... 328 13.14 ethernet frame tr ansmit errors.............................................................................. 329 13.15 frame length support ............................................................................................ 331 13.16 frame data and byte format.................................................................................. 333 13.17 frame filt ering ........................................................................................................ 340 13.18 pause flow control ............................................................................................... 344 13.19 ethernet mac receive fifo overrun co ndition .................................................... 348 13.20 using the performance monitoring features .......................................................... 349 13.21 interrupt handling.................................................................................................... 349 13.22 jtag support.......................................................................................................... 350 13.23 receive pcs layer error ha ndling......................................................................... 355 13.24 transmit pcs layer error handling........................................................................ 358 13.25 mdio access........................................................................................................... 359 14 functional timing.............................................................................................................. .. 361 14.1 pl4 interface data path and fifo status timing................................................... 361 14.2 xsbi functional timing........................................................................................... 362 15 absolute maxi mum ratings ................................................................................................ 364 16 d.c. characteristics ........................................................................................................... . 365
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 7 document no.: pmc-2001304, issue 7 17 microprocessor interface timing characteristics................................................................ 368 18 ac timing characteristics................................................................................................... 371 18.1 pl4 interface timing ............................................................................................... 371 18.2 system miscell aneous timing................................................................................. 377 18.3 xsbi interfac e timing ............................................................................................. 378 18.4 jtag port timing .................................................................................................... 379 18.5 mdio/mdc timing .................................................................................................. 380 19 thermal info rmation............................................................................................................ 381 19.1 power requi rements............................................................................................... 382 20 mechanical in formation....................................................................................................... 384 21 ordering in format ion ........................................................................................................... 386 notes 387
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 8 document no.: pmc-2001304, issue 7 list of registers register 0x0000h:pm 3392 identif ication .................................................................................... 96 register 0x0001h:pm339 2 product revision............................................................................. 97 register 0x0002h:pm 3392 configuration and reset c ontrol .................................................... 98 register 0x0003h: pm3392 master in terrupt status ................................................................. 100 register 0x0004h:pm 3392 device status ................................................................................ 103 register 0x0005h:pm 3392 global performanc e monitor update ............................................ 105 register 0x0006h:md io command register ........................................................................... 106 register 0x0007h:mdio interrupt ma sk register..................................................................... 108 register 0x0008h:mdio interrupt register .............................................................................. 109 register 0x0009h:mmd phy address register....................................................................... 110 register 0x000ah: mmd control addres s data re gister.......................................................... 111 register 0x000bh:mdio read status data register............................................................... 112 register 0x0100h: xsbi wrapper configur ation re gister......................................................... 113 register 0x0104h:xsbi interrupt status................................................................................... 116 register 0x0107h:xsbi interrupt enable2............................................................................. 118 register 0x0108h:xsbi interrupt enable3............................................................................. 119 register 0x0109 h:xsbi rxoolv ............................................................................................ 120 register 0x010ah:xsbi analog debug register...................................................................... 121 register 0x2040h:rxxg configuration 1 ................................................................................. 122 register 0x2042h:rxxg configuration 3 ................................................................................. 125 register 0x2043h: rxxg in terrupt ............................................................................................ 127 register 0x2044 h:rxxg status ............................................................................................... 129 register 0x2045h:rxxg maximum fr ame length .................................................................. 130 register 0x2046h:rxxg sa[ 15:0] ? stati on address .............................................................. 131 register 0x2047h:rxxg sa[ 31:16] ? stati on address ............................................................ 132 register 0x2048h:rxxg sa[ 47:32] ? stati on address ............................................................ 133 register 0x2049h: rxxg receive fi fo threshold .................................................................. 134 register 0x204ah:rxxg exac t match addres s 0 low word................................................... 137 register 0x204bh:rxxg exac t match addres s 0 mid word ................................................... 138 register 0x204ch:rxxg exac t match addres s 0 high word.................................................. 139 register 0x204dh:rxxg exac t match addres s 1 low word .................................................. 140 register 0x204eh: rxxg exact match a ddress 1 mi d word .................................................. 141 register 0x204fh:rxxg exac t match addres s 1 high word .................................................. 142
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 9 document no.: pmc-2001304, issue 7 register 0x2050h:r xxg exact match a ddress 2 lo w wo rd ................................................... 143 register 0x2051h:r xxg exact match a ddress 2 mi d word.................................................... 144 register 0x2052h:r xxg exact match a ddress 2 hi gh word .................................................. 145 register 0x2053h:r xxg exact match a ddress 3 lo w wo rd ................................................... 146 register 0x2054h:r xxg exact match a ddress 3 mi d word.................................................... 147 register 0x2055h:r xxg exact match a ddress 3 hi gh word .................................................. 148 register 0x2056h:r xxg exact match a ddress 4 lo w wo rd ................................................... 149 register 0x2057h:r xxg exact match a ddress 4 mi d word.................................................... 150 register 0x2058h:r xxg exact match a ddress 4 hi gh word .................................................. 151 register 0x2059h:r xxg exact match a ddress 5 lo w wo rd ................................................... 152 register 0x205ah:rxxg exac t match addres s 5 mid word ................................................... 153 register 0x205bh:rxxg exac t match addres s 5 high word.................................................. 154 register 0x205ch:rxxg exac t match addres s 6 low word .................................................. 155 register 0x205dh:rxxg exac t match addres s 6 mid word ................................................... 156 register 0x205eh:rxxg exac t match addres s 6 high word.................................................. 157 register 0x205fh: rxxg exac t match addres s 7 low word.................................................. 158 register 0x2060h:r xxg exact match a ddress 7 mi d word.................................................... 159 register 0x2061h:r xxg exact match a ddress 7 hi gh word .................................................. 160 register 0x2062h:rxxg exact matc h vid 0 ........................................................................... 161 register 0x2063h:rxxg exact matc h vid 1 ........................................................................... 162 register 0x2064h:rxxg exact matc h vid 2 ........................................................................... 163 register 0x2065h:rxxg exact matc h vid 3 ........................................................................... 164 register 0x2066h:rxxg exact matc h vid 4 ........................................................................... 165 register 0x2067h:rxxg exact matc h vid 5 ........................................................................... 166 register 0x2068h:rxxg exact matc h vid 6 ........................................................................... 167 register 0x2069h:rxxg exact matc h vid 7 ........................................................................... 168 register 0x206ah: rxxg multicast hash low word ............................................................. 169 register 0x206bh:rxxg mu lticast hash midlow word......................................................... 170 register 0x206ch:rxxg mult icast hash mi dhigh word........................................................ 171 register 0x206dh:rxxg mu lticast hash high word ............................................................. 172 register 0x206eh:rxxg a ddress filter contro l 0 ................................................................... 173 register 0x206fh:rxxg a ddress filter contro l 1 ................................................................... 175 register 0x2070h:rxxg a ddress filter contro l 2 ................................................................... 177 register 0x2 080h:r64b66b c onfigurat ion............................................................................... 178 register 0x2 081h:r64b66b in terrupt mask ............................................................................. 179
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 10 document no.: pmc-2001304, issue 7 register 0x2082 h:r64b66b inte rrupt st atus ........................................................................... 181 register 0x2083h: r64b66b status .......................................................................................... 183 register 0x2 084h:r64b66b e rror_fram e_cnt ............................................................... 185 register 0x2085h: r64b66b frame_lo ck_count[15:0].................................................... 186 register 0x2086 h:r64b66b hi_ ber_cnt[4:0]....................................................................... 187 register 0x2087h: r 64b66b jitter_ cnt[15:0] .................................................................... 188 register 0x2100h: mstat control............................................................................................ 189 register 0x2101h:mstat counter roll over 0 ......................................................................... 190 register 0x2102h:mstat counter roll over 1 ......................................................................... 191 register 0x2103h:mstat counter roll over 2 ......................................................................... 192 register 0x2104h:mstat counter roll over 3 ......................................................................... 193 register 0x2105h:msta t interrupt mask 0 ............................................................................. 194 register 0x2106h:msta t interrupt mask 1 ............................................................................. 195 register 0x2107h:msta t interrupt mask 2 ............................................................................. 196 register 0x2108h:msta t interrupt mask 3 ............................................................................. 197 register 0x2109h:mstat counter writ e address................................................................... 198 register 0x210ah:mstat c ounter write data low ................................................................ 199 register 0x210bh:mstat c ounter write da ta middle ............................................................ 200 register 0x210ch:mstat c ounter write data high ............................................................... 201 register 0x2110h to 0x 21e6h:mstat receive stat istical counters? low.............................. 202 register 0x2110h to 0x21e6h:mstat receive stat istical counters? middle.......................... 203 register 0x2110h to 0x 21e6h:mstat receive stat istical counters? high ............................. 204 register 0x2200h:iflx global configuration register............................................................. 215 register 0x2201h:iflx channel provision............................................................................... 216 register 0x2209h:iflx fifo overfl ow enable ........................................................................ 217 register 0x220ah:iflx fi fo overflow interrupt...................................................................... 218 register 0x220dh:iflx i ndirect channe l address................................................................... 219 register 0x220eh:iflx indirect logical fifo low limit & provision ...................................... 220 register 0x220fh:iflx indire ct logical fifo high li mit ......................................................... 221 register 0x2210h:iflx indirect full/almost full status & limit ............................................... 222 register 0x2211h:iflx indirect empty/almost empty status & limit ...................................... 223 register 0x2240h:pl4mos configuration register ................................................................. 224 register 0x2241h: pl4mos reserved...................................................................................... 226 register 0x2242h:p l4mos fairness mask ............................................................................. 227 register 0x2243h:pl4mos maxburst1 register ..................................................................... 228
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 11 document no.: pmc-2001304, issue 7 register 0x2244h:pl4mos maxburst2 register ..................................................................... 229 register 0x2245h:pl4mos transfer size register ................................................................. 230 register 0x2 280h:pl4odp c onfiguration ................................................................................ 231 register 0x2 282h:pl4odp in terrupt mask .............................................................................. 233 register 0x2283h: pl4odp in terrupt ........................................................................................ 234 register 0x2284h:p l4odp configurati on max_t register .................................................... 235 register 0x2300 h:pl4io lock de tect status ........................................................................... 237 register 0x2301 h:pl4io lock de tect change......................................................................... 239 register 0x2 302h:pl4io lock detect mask............................................................................. 241 register 0x2303 h:pl4io lock de tect limits ............................................................................ 243 register 0x2304 h:pl4io calenda r repetit ions........................................................................ 244 register 0x2305h:p l4io config uration .................................................................................... 245 register 0x3040h:txxg c onfiguration r egister 1................................................................... 250 register 0x3042h:txxg c onfiguration r egister 3................................................................... 253 register 0x3043h: txxg interrupt ............................................................................................ 255 register 0x3044h:txxg status register ................................................................................. 257 register 0x3045h:txxg tx_maxfr transmit max frame size register.............................. 258 register 0x3046h:txxg tx_minfr tr ansmit min frame size register................................ 259 register 0x3047h:txxg sa[ 15:0] station address ................................................................. 260 register 0x3048h:txxg sa[ 31:16] stati on address ............................................................... 261 register 0x3049h:txxg sa[ 47:32] stati on address ............................................................... 262 register 0x304dh:txxg pause_ time ? pause ti mer register ....................................... 263 register 0x304eh:txxg pause_ival pause timer inte rval register ................................ 264 register 0x3052h:txxg pause quant um value configur ation register ................................ 265 register 0x3080h:t64b 66b configur ation 1 ............................................................................ 266 register 0x3083h: t64b66b status .......................................................................................... 268 register 0x3085h: ji tter test seed a 3 ............................................................................ 270 register 0x3086h: ji tter test seed a 2 ............................................................................ 271 register 0x3087h: ji tter test seed a 1 ............................................................................ 272 register 0x3088h: ji tter test seed a 0 ............................................................................ 273 register 0x3089h: ji tter test seed b 3 ............................................................................ 274 register 0x308ah: ji tter test seed b 2 ........................................................................... 275 register 0x308bh: ji tter test seed b 1 ........................................................................... 276 register 0x308ch: ji tter test seed b 0 ........................................................................... 277 register 0x3200h:eflx global config uration.......................................................................... 278
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 12 document no.: pmc-2001304, issue 7 register 0x3201h:eflx ercu global status.......................................................................... 279 register 0x3202h:eflx i ndirect channel address .................................................................. 280 register 0x3203h:ef lx indirect logical fifo low limit......................................................... 281 register 0x3204h:ef lx indirect logical fifo high limit ........................................................ 282 register 0x3205h:eflx indirect full/almost-f ull status and limit.......................................... 283 register 0x3206h:eflx indirect empty/almost-e mpty status and limit ................................. 284 register 0x3207h:eflx indirect fifo cu t-through th reshold ............................................... 285 register 0x320ch:eflx fifo overflow e rror e nable ............................................................. 286 register 0x320dh: eflx fifo overflow erro r indication ........................................................ 287 register 0x3210h:eflx channel pr ovision ............................................................................. 288 register 0x3 280h:pl4idu co nfiguration.................................................................................. 289 register 0x3281h: pl4idu status............................................................................................. 290 register 0x3 282h:pl4idu in terrupt mask ................................................................................ 291 register 0x3283h: pl4idu in terrupt.......................................................................................... 292 pm3392 test r egister 0......................................................................................................... ... 294 pm3392 test r egister 4......................................................................................................... ... 295
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 13 document no.: pmc-2001304, issue 7 list of figures figure 1 10 gigabit et hernet refere nce model......................................................................... 21 figure 2 router - 10g port capable ......................................................................................... 23 figure 3 no rmal mode......................................................................................................... ...... 24 figure 4 loopba ck paths ...................................................................................................... .... 25 figure 5 ba ll view 1......................................................................................................... .......... 28 figure 6 ba ll view 2......................................................................................................... .......... 29 figure 7 ba ll view 3......................................................................................................... .......... 29 figure 8 rx sy nc state ma chine ............................................................................................ 59 figure 9 receiv e state machine ............................................................................................... 60 figure 10 rx ber state machine............................................................................................. 62 figure 11 state mach ine of a fi fo ch annel ............................................................................ 68 figure 12 tx processing steps for 66- bit codes .................................................................... 76 figure 13 input obse rvation cell (in_cell) .......................................................................... 301 figure 14 output cell (out_cell) ........................................................................................ 301 figure 15 bi-directi onal cell (io_ce ll) .................................................................................. 302 figure 16 layout of output e nable and bi-direc tional cells ................................................... 302 figure 17 pos-phy level 4 in terfaces................................................................................... 305 figure 18 pos-phy level 4 slave cl ocking mode ................................................................ 306 figure 19 pos-phy level 4 master cl ocking mode .............................................................. 307 figure 20 sample fifo thresholds ........................................................................................ 312 figure 21 pl4io data in state diagram ................................................................................. 317 figure 22 pl4io fifo status stat e diagram ......................................................................... 319 figure 23 pl4io stat us in stat e diagr am............................................................................... 320 figure 24 boundary scan arch itecture ................................................................................... 351 figure 25 tap controller finite stat e machine....................................................................... 353 figure 26 expected packet formats ....................................................................................... 356 figure 27 pl4 interface data path functional timing ............................................................ 361 figure 28 pl4 interface fifo status functi onal timing......................................................... 362 figure 29 ingre ss timing diagram .......................................................................................... 362 figure 30 egress timing diagram........................................................................................... 363 figure 31 microprocessor interface re ad timing ................................................................... 368 figure 32 microprocessor interface wri te timing ................................................................... 370 figure 33 pl4 bus output status ac ti ming diagram ........................................................... 374
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 14 document no.: pmc-2001304, issue 7 figure 34 pl4 bus input st atus ac timi ng diagram.............................................................. 375 figure 35 pl4 bus output status ac ti ming diagram ........................................................... 376 figure 36 pl4 bus input st atus ac timi ng diagram.............................................................. 376 figure 37 system miscel laneous timing diagram.................................................................. 377 figure 38 line in terface timing.............................................................................................. . 378 figure 39 jtag port interfac e timing..................................................................................... 379 figure 40 mdc / mdio physical timing ................................................................................. 380 figure 41 896 pin fcbga -31x31 mm body - (3 m substrate) ............................................ 384 figure 42 896 pin fcbga -31x31 mm body - (hdb u substrate) ....................................... 385
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 15 document no.: pmc-2001304, issue 7 list of tables table 1 s/uni-1x1 0ge abbreviations....................................................................................... 17 table 2 s/uni-1x10ge line side signaling interface............................................................... 31 table 3 s/uni-1x10ge syst em side signalin g interface ......................................................... 34 table 4 ecbi si gnals and m dc/mdio...................................................................................... 39 table 5 jtag and reserved signals ........................................................................................ 41 table 6 s/uni-1 x10ge analog pins ......................................................................................... 43 table 7 digital power and ground ............................................................................................ 44 table 8 prea mble checking .................................................................................................... .. 64 table 9 range, size and crc result processing.................................................................... 64 table 10 receive st atistics counters ....................................................................................... 78 table 11 transmit statistics counters ...................................................................................... 78 table 12 regist er memory map ................................................................................................ 80 table 13 normal mo de register map ....................................................................................... 81 table 14 cut_thru_t hres packet sizes .......................................................................... 135 table 15 mstat c ounter desc ription .................................................................................... 205 table 16 interpac ket gap encoding ....................................................................................... 251 table 17 instruction regi ster (length - 3 bits)........................................................................ 295 table 18 identi fication register............................................................................................. .. 296 table 19 boundary scan r egister .......................................................................................... 296 table 20 pl4 bus data transfer rate for non-bloc king operation ...................................... 308 table 21 transmit inte rpacket gap encoding ........................................................................ 326 table 22 pm3392 minimum tran smit frame si ze padding.................................................... 328 table 23 std 802-1990, figur e 5-3 universa l address ........................................................... 334 table 24 mac frame format.................................................................................................. 336 table 25 pm3392 data order on pl4 in terface, non-vlan ethernet frame ....................... 337 table 26 pm3392 data order on pl4 in terface, vlan et hernet frame type ...................... 338 table 27 ten gigabit et hernet frame example...................................................................... 339 table 28 address filter resu lt in non-prom iscuous mode .................................................... 343 table 29 address filter in promiscuous mode ....................................................................... 343 table 30 pause cont rol frame format................................................................................. 345 table 31 iflx fifo settings for lossless flow control ............................................................ 346 table 32 pause frame programmable control .................................................................... 347 table 33 maxi mum rati ngs..................................................................................................... 364
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 16 document no.: pmc-2001304, issue 7 table 34 core s upply voltage specs ..................................................................................... 364 table 35 i/o s upply voltage specs ........................................................................................ 364 table 36 d.c. characteristics ................................................................................................ . 365 table 37 microprocessor inte rface multiplex ed read ti ming ................................................. 368 table 38 microprocessor interface wri te access.................................................................... 369 table 39 lvds electr ical specifications ................................................................................. 371 table 40 reference clock timing spec ifications for di vby2 (pl4_refclk) ........................ 371 table 41 reference clock timing spec ifications for di vby4 (pl4_refclk) ........................ 372 table 42 output data timing (rdclk, rctl, rdat) ........................................................... 373 table 43 input data timi ng (tdclk, tc tl, tdat) ............................................................... 373 table 44 output status timing (tsclk, tstat[1:0]) ............................................................ 374 table 45 input status ti ming (rsclk, rs tat[1:0]) .............................................................. 375 table 46 output status timing (tsclk, tstat[1:0]) ............................................................ 375 table 47 input status ti ming (rsclk, rs tat[1:0]) .............................................................. 376 table 48 system miscellaneou s timing.................................................................................. 377 table 49 xsbi in terface timing .............................................................................................. 378 table 50 jtag port interface................................................................................................. . 379 table 51 mdc / mdio interface timing .................................................................................. 380 table 52 outside plant thermal in formation .......................................................................... 381 table 53 device compact model 3 ........................................................................................... 381 table 54 heat si nk requirements .......................................................................................... 381 table 55 powe r consumption ................................................................................................. 382 table 56 orderin g information ................................................................................................ 386
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 17 document no.: pmc-2001304, issue 7 1 definitions table 1 s/uni-1x10ge abbreviations pl4 short hand notation for pos- phy level 4 system interface pl4idu pl4 input data unpacker pl4odp pl4 output data packer pl4io pl4 input and output interface pl4 input pos-phy level 4 input interface: rela tes to data impressed on tdclk+/- and tdat[15:0]+/- pins. pl4 output pos-phy level 4 output interface: re lates to data impressed on rdclk+/- and rdat[15:0]+/- pins. pl4mos pl4 multi-stream output scheduler eflx egress fifo iflx ingress fifo txxg 10 gbit/s transmit mac rxxg 10 gbit/s receive mac r64b66b 10.3 gbit/s receive pcs t64b66b 10.3 gbit/s transmit pcs xsbi 10.3 gbit/s serial interface phy physical layer interface lan phy designated by ieee 10gigabit ethernet stand ards committee as one of two variants of the 10ge standard intended for applications in which sonet compatibility is not required and data rates should be maximized. data frame or frame consist of destination address, source a ddress, length field, logical link control (llc) data, pad, and frame check sequence. full duplex a mode of operation that supports simult aneous communication between a pair of stations, provided that the physical layer is capable of supporting simultaneous transmission and reception without interference. ipg inter-packet gap (ipg): a delay or time gap between physical packets. mib management information base (mib): a r epository of information to describe the operation of specific network device. mac media access control (mac): the data link sub-layer that is responsible for transferring data to and from the physical layer. packet the logical unit of data transferred across the pos-phy level 3 interface. this generally corresponds to the data frame as defined previously, although the crc may or may not be present in the pos-phy level 3 egress direction. physical packet consists of a data frame as defined pr eviously, preceded by the preamble and the start frame delimiter, encoded, as appropriate, for the physical layer (phy) type. pos-phy saturn compatible packet over sonet inte rface specification for physical layer devices. pos-phy level 4 defines an interface for bit rates up to and including 10gbit/s. sof start of frame. sop start of packet. eof end of frame.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 18 document no.: pmc-2001304, issue 7 eop end of packet. jumbo frame in the context of this document, jumbo frame refers to a data frame (see definition in this table) that has a frame size in number of octets that meets all of the following criteria: 1. it is greater than the maximum 802.3 st andard specified frame length (1518 octets for untagged frames and 1522 octets for tagged frames) 2. it is less than or equal to the maximum co nfigurable receive/transmit frame size (for receive, see rxxg register 2045h, re ceive max frame length; for transmit, see txxg register 3045h, transmit max frame length). 3. the frame length is less than or equal to 9600 octets other than the number of octets in the data frame, a jum bo frame otherwise meets all the requirements as outlined in the 802.3 ethernet standard. prbs pseudo random bit sequencing
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 19 document no.: pmc-2001304, issue 7 2 features 2.1 general ? implements 10 gigabit ethernet lan phy according to ieee 802.3ae standard. ? provides direct connection to optics via a 16-bit by 644.53125mhz ieee 802.3ae xsbi line-side interface. ? provides standard ieee 802.3ae 10 gigabit et hernet media access controller (10gmac) for frame verification. ? implements ieee 802.3ae standard 64b/66b physical coding sub-layer (pcs). ? provides ieee 802.3ae standard square wave and pseudo-random test pattern generation and checking. ? provides saturn? pos-phy level 4 ? 16-bit lvds system interface for 10 gigabit ethernet applications. ? line-side and system side loopback for system level diagnostic capability. ? internal 128 kbyte ingress fifo and 16kbyte egress fifo to accommodate system latencies. ? provides a standard 5 signal ieee 1149.1 jt ag test port for boundary scan board test purposes. ? provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring. ? low power 1.8v cmos core logic with 3.3v cmos/ttl compatible digital inputs and digital outputs. ? industrial temperature range (-40c to +85c) ambient. ? 896 pin fcbga package. 2.2 10 gigabit ethernet mac ? provides an ieee 802.3ae standard10 gigabit mac for ethernet frame handling. ? provides mapping to insert/extract ethernet frames into/from the ieee 802.3ae standard physical coding sub-layer (pcs). ? verifies frame integrity (fcs and length checks). ? supports 64b/66b-based frame delineation. ? supports ethernet 2.0, ieee 802.3 llc a nd ieee 802.3 snap/llc encoding formats including vlan tagged frames. ? in the receive direction, supports frame de lineation, frame integrity (fcs and length) checks, frame filtering and passing based on erre d frames, 64 byte minimum frame size and a 9600 byte maximum frame size.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 20 document no.: pmc-2001304, issue 7 ? supports address filtering on all standard ethernet size frames up to 9.6k bytes. ? in the transmit direction, supports frame ge neration (preamble, crc), minimum frame size padding up to 64 bytes, truncation of over-length frames. ? supports multicast and unicast address filtering using eight exact match filters and promiscuous mode. frames can be filtered based on sa, sa/vid, da, or da/vid. provides 64-bin hash based algorith m to filter multi-cast addresses. ? with in-band pause flow control the pm3392 implements 3 km lossless flow control for 9600 byte frames and 5 km lossless flow control for 1518 byte frames. ? provides support for out-of-band flow control for upper layer device by using dedicated pins or host signaling to cause generation of a pause frame. 2.3 statistics ? provides statistic counters to support o ethernet mib ieee 802.3-2000, clause 30 and 802.3ae o compatible snmp interface group mib, rfc 1213 mib ii & rfc 2233 smiv2 o rmon statistics group mib, rfc 1757 o ethernet-like mib, rfc 2665 ? provides 40-bit wide counters for statistics 2.4 pos-phy level 4 interface ? designed to transmit cells, packets, or frames between physical and data-link layer devices. ? compliant with the following standards: o atm forum ? frame based atm interface level 4 (atmf0161.00) o optical internetworking forum ? system physical interface level 4 phase ii (oif2000.088)
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 21 document no.: pmc-2001304, issue 7 3 applications ? metro pop (point of presence) ? uplink cards ? ip pop router ? ip services ? multi-service switch figure 1 10 gigabit ethernet reference model wis mac control (optional) media access control (mac) reconcilliation physical coding sublayer (pcs) physical medium attachment (pma) physical medium dependant (pmd) upper layer 64b/66b codec sonet framer & scrambler serdes
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 22 document no.: pmc-2001304, issue 7 4 references 1. oif ? oif99.102, ?proposal for a common electrical interface between sonet framers and sonet serializer / deserializer parts for sts-192/stm-64 interfaces.? july 1999. 2. oif ? oif00.026.0, ?spi-4 phase ii.? baseline text. 3. pmc-991635, ?pos phy level 4, saturn interface specification for packet and cell transfer between physical layer and link layer devices for oc-192 sonet/sdh and 10 gbit/s ethernet applications?, issue 4, april 2000. 4. ieee 802.3aestandard; media access control (mac) parameters, physical layer, and management parameters for 10 gbit/s operation 5. ieee std. 802.3, 2000 edition; carrier sense multiple access with collision detection (csma/cd) access method and physical layer specification 6. rfc 1757 remote network monitoring management information base 7. rfc 1213 management information base fo r network management of tcp/ip-based internets: mib-ii 8. rfc 2233 the interfaces group mib using smiv2 9. rfc 2665 definitions of managed objects for the ethernet-like interface types 10. pmc-sierra, inc, pmc-2010502 pos-ph y level 4 frequently asked questions 11. pmc-sierra, inc., ?pos-phy level 4 static alignment design considerations application note?, issue 1, march 2001 12. pmc-sierra, inc., pmc-2010198 ?pmc pl4 compliance statement?, issue 1, february 2001 13. pmc-sierra, inc., pmc-2001305 ?pos-p hy level 4 clocking and initialization application note?, issue 1, november 2000 14. pmc-sierra, inc., pmc-2020518 ?pl4 electrical spec clarifications application note?, issue 1, march 2002
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 23 document no.: pmc-2001304, issue 7 5 application examples the pm3392 s/uni?-1x10ge device is applicable to equipment implementing 10-gigabit ethernet lan phy interfaces. the s/uni-1x10g e provides physical layer and mac layer termination for connections between edge, ente rprise edge, and core routers, multi service switches and transport equipment at the 10 gigabit rates. one of the most likely locations for initial deployment of 10ge lan phy is within the s uper-pop. router to router connections is expected to be early adopters of 10ge lan conn ections. server farm connections will also provide a potential application for 10ge. it is also expected that 10ge wan phy will find application in connecting pops to s onet or dwdm transport equipment. figure 2 router - 10g port capable 10 gigabit ethernet line card 10 x gigabit ethernet line card 1 x oc-192 line card (pos/atm/10g enet) s/uni 9953 atm interworking or l2/l3 processor traffic manage integrated optics packet/atm switching core s/uni 10xge traffic manage x10 l2/l3 processor l2/l3 processor traffic manage integrated optics 4 x oc-48 line card (pos/atm) crsu 4x2488 optics s/uni 9953 traffic manage optics optics optics atm interworking processor or l2/l3 processor optics optics 10 gigabit ethernet line card l2/l3 processor traffic manage xenpak optics s/uni 1x10ge s/uni 1x10ge- xp
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 24 document no.: pmc-2001304, issue 7 6 block diagram the following block diagrams give a high level view of the pm3392 s/uni-1x10ge. the first depicts the device in normal mode exploiting a ll major paths. the second shows two distinct loop-back paths, system side and line side. figure 3 normal mode t c t l + / - t d a t [ 1 5 : 0 ] + / - r s t a t [ 1 : 0 ] pos-phy level 4 txdata[4:1][3:0]+/- d [15:0] intb a [14:0] rstb ale csb wrb rdb microprocessor interface trstb tms tdi tck tdo jtag rctl+/- rdclk+/- tsclk tstat[1:0] rdat[15:0]+/- pl4io pl4mos pl4idu pl4odp iflx eflx pcs layer tx decoder t64b66b rx encoder r64b66b ethernet statistics ten gigabit macs rxxg txxg p l 4 _ r c l k + / - oifs_atb[1:0] pl4_res pl4_resk oifs_res oifs_resk rxclk[4:1]+/ - rxdata{4:1][3:0]+/- txclk_src[4:1]+/- txclk[4:1]+/ - sync_err oifs wrapper oifs analog only pl4_atb[5:0] t d c l k + / - paused mpgm phase_err phase_init vclk[6:1] mdio mdc dtrb vclk_forceb r s c l k pause refsel[1:0] rx_sysclk2 rx_los nc[11:1] tx_sysclk2 cpref_clk figure 3 gives a high-level block view of the suni-1x10ge. all major data paths are shown with the appropriate signaling interfaces.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 25 document no.: pmc-2001304, issue 7 figure 4 loopback paths tctl+/- tdat[15:0]+/- rstat[1:0] pos-phy level 4 txdata[4:1][3:0]+/- d [1 5: 0] in tb a [1 4: 0] r st b al e c sb w r b r d b microprocessor interface tr st b t m s td i tc k td o jtag rctl+/- rdclk+/- tsclk tstat[1:0] rdat[15:0]+/- pl4io pl4mos pl4idu pl4odp iflx eflx pcs layer tx decoder t64b66b rx encoder r64b66b ethernet statistics ten gigabit macs rxxg txxg pl4_rclk+/- oifs_atb[1:0] pl4_res pl4_resk oifs_res oifs_resk rxclk[4:1]+/ - rxdata{4:1][3:0]+/- txclk_src[4:1]+/- txclk[4:1]+/ - sync_err oifs wrappe r oifs analog only pl4_atb[5:0] tdclk+/- paused mp g m phase_err phase_init v cl k[ 6: 1] m di o m d c dt r b v cl k_ f o r c rsclk pause refsel[1:0] rx_sysclk2 rx_los nc[11:1] tx_sysclk2 c p r ef _ c lk system side loopback lineside loopback figure 4 shows 2 possible loopback paths that are supported in the pm3392. the device supports both system side loopback through the xsbi wrapper, line side loopback through the pl4io and system side loopback through the pl4io.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 26 document no.: pmc-2001304, issue 7 7 description the pm3392 s/uni-1x10ge saturn user netw ork interface is a monolithic integrated circuit that implements all the required f unctions of a 10 gigabit ieee 802.3ae standard compatible ethernet lan physical layer device (lan phy). the s/uni-1x10ge ethernet phy device consists of a ten gigabit sixteen -bit interface (xsbi) block, a 64b66b based physical coding sub-layer, a 10-gigabit mac, and a pos-phy level 4 interface. the s/uni-1x10ge transmits and receives ethernet packets via connections to an optical module. the xsbi block accomplishes the interface bus between the optical module and the pm3392. the xsbi is derived from the oif99.102.5 sfi-4 specification. the xsbi bus uses low voltage differential signaling (lvds) fo r both clock and data receiver/transmitters. sixteen pairs of lvds data signals are provided in the transmit channel and another sixteen pairs in the receive channel. the source clock fo r the data receivers is rxclk+/- and is used for the internal reference. in the transmit dir ection, a single reference clock, txclk_src+/- is provided for the 16 data channels. the source lvds clock that is transmitted aligned with the data. the lvds reference clock txclk_src, an input to the pm3392, is provided by the serdes to the xsbi as a reference clock for the pcs layer, the mac, and the transmit framer functionality. when the clock rate is 644.53125mhz, an aggregate of 10320mbit/s (16x644.53125mbit/s) is transferred in each direction. the s/uni 1x10ge txxg block processes all outgoing ethernet frames and performs the mac functionality on the egress path. the txxg provides ethernet framing, insertion of an 8- byte preamble/start frame delimiter sequence, plus computation and optional insertion of a 32- bit fcs. frame timing is provided relative to the system clock reference input. the transmit framer will insert the correct programmable inter -frame gap between frames to ensure that the lan-mode operation conforms to the ieee 802.3 specification. the inter-frame gap, preamble, fcs generation, and error checking features of the transmit framer can be configured by means of internal configuration registers accessible via a microprocessor interface. it provides pause frame generation and insertion. the pm3392 also supports an external ?pause? pin so that the system can force the mac to send pause frames. generated pause frames are multiplexed into the outgoing frame stream in be tween data frames, with the proper spacing. the s/uni 1x10ge rxxg block processes all incoming ethernet packet streams while performing basic frame checks. the mac provid es ethernet framing detection, framing to the standard preamble/sfd sequence, removal of the preamble/sfd, checking of the 32-bit crc field and frame validation (marking of erred frames for discard). frame timing checks are relative to the receive input reference clock. th e rxxg will verify that the inter-frame gap does not fall below a pre-set minimum and will filter frames that violate this restriction when used in lan-mode devices. optional received frame filtering allows frames to be discarded if they are found to contain length or crc errors. the rxxg implements a 2048-byte full-frame buffer to facilitate this filtering. jumbo frames that are e rred will not be filtered but marked as an error and passed on. jumbo frames will however, be address filtered.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 27 document no.: pmc-2001304, issue 7 the rxxg supplies received frame stream parsing and pause mac control frame detection, validation and extraction. the pause timer fiel ds of received pause frames are extracted and sent to flow control logic. if enabled the flow control logic will pause data frames from begin transmitted onto the xsbi interface and assert the external ?paused? pin for use by the system. when the paused pin is asserted this means that the txxg is in a paused state and is no longer transmitting data frames. the rxxg checks every received frame against the ieee 802.3 frame error criteria and updates the appropria te statistics counters, which can be used to implement the standard ethernet mib for link management. configuration and status maintenance, the minimum ifg, maximum frame size, preamble checking and erred frame discard functions, can be configured by means of internal configuration registers. status registers are also implemented by the rxxg to permit a host cpu to monitor its functions. the frame check sequence is optionally verified for correctness and the extract ed packets are placed in a receive fifo. a full suite of ethernet st atistics are counted and provided for performance monitoring. the pl4 interface provides a 16-bit wide data bus , an in-band control stream, a single control signal, and a dual phase source synchronous clock in the forward path. all forward path signals are differential lvds. the clock signal is either loop timed from the tdclk+/- or internally generated using the pl4_rclk+/- re ference input. the control signal is used to identify the in- band control words. in the return path, the pl4 interface provides a two-bit fifo status bus with associated clock. these status signals ar e provided to the pl4mos block to allow it to make scheduling decisions. in the case of the pm 3392, decisions are limited to releasing data based on credit information. in addition, the r eceive pl4 interface allows for the transmission of a training sequence to allow for dynamic de-skewing by a sink entity. data must contain a sufficient training pattern density to allow re liable operation of the da ta recovery and de- skewing units. the pl4 interfaces transfer un-en coded nrz data streams. consequently there may be arbitrarily long runs of consecutive zeros or ones. the transmit pl4 interface is capable of properly recovering data once training has completed. the receive pl4 interface implements the pl4 protocol as described in pmc-991635. the pl4 interface consists of a phy interface (pl4io ), output data packer (pl4odp), input data packer (pl4idu), and multi-stream output scheduler (pl4mos). the pl4odp encapsulates the outgoing data stream originating at the iflx fifo interface. the pl4idu unpacks the incoming pl4 data stream and presents the fra med data to the eflx fifo. the pl4mos is used to generate transfer requests to the i ngress fifo using a credit based scheduling scheme.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 28 document no.: pmc-2001304, issue 7 8 pin diagram the pm3392 is packaged in an 896 flip chip ba ll grid array package. the body size is 31mm by 31mm with a 1.0mm ball pitch. figure 5 ball view 1 30 29 28 27 26 25 24 23 22 21 a vddi tdat_n[1] tdat_n[4] tdclk_n tdat_n[9] vss vddo tdat_n[14] tdat_n[15] a b vddi vddi vss tdat_p[1] tdat_p[4] tdclk_p tdat_p[9] vddo vss tdat_p[14] b c pl4_avdh[2] vss vss vddo tdat_n[0] tdat_n[5] tdat_n[8] tdat_n[12] vss vddo c d pl4_atb[3] pl4_avdh[1] vddo vddo vss tdat_p[0] tdat_p[5] tdat_p[8] tdat_p[12] vddo d e pl4_resk pl4_atb[1] pl4_avdl[3] vss vss vddi tdat_n[3] tdat_n[6] tdat_n[10] tdat_n[11] e f rdat_p[0] pl4_res pl4_avdl[2] pl4_avdh[0] vddi vddi vss tdat_p[3] tdat_p[6] tdat_p[10] f g vss rdat_n[0] pl4_atb[0] pl4_avdl[1] pl4_rclk_p vss vss vddi tdat_n[2] tdat_n[7] g h vddo vddo rdat_p[1] pl4_atb[2] pl4_atb[5] pl4_rclk_n vddi vddi vss tdat_p[2] h j rdat_p[3] vss vss rdat_n[1] pl4_avdh[3] pl4_atb[4] vss vss vss vddi j k rdat_p[6] rdat_n[3] vddo vddo rdat_p[2] vss vddo vddo vddi vddi k l rdat_p[7] rdat_n[6] rdat_p[4] vss vss rdat_n[2] vss vss vddi vss l m rdat_p[8] rdat_n[7] rdclk_p rdat_n[4] vddo vddo vddi vddi vddi vddi m n vddi rdat_n[8] rdat_p[9] rdclk_n rdat_p[5] vss vss vss vddo vddi n p vss vss rdat_p[10] rdat_n[9] rdat_p[11] rdat_n[5] vddo vddo vddo vddo p r vddo vddo vddi rdat_n[10] vss rdat_n[11] vss vss vss vddo r t vddo vddi vddi rdat_n[13] vss refsel[0] vss vss vss vddo t u vss vss rdat_p[13] rdat_n[14] refsel[1] vss vddo vddo vddo vddo u v vddi rdat_n[12] rdat_p[14] nc5 vss vss vss vss vddo vddi v w rdat_p[12] rdat_n[15] nc6 rstat[1] vddo vddo vddi vddi vddi vddi w y rdat_p[15] rctl_n rstat[0] vss vss vss vss vss vddi vss y aa rctl_p pause vddo vddo vddi vddi vddo vddo vddi vddi aa ab rsclk vss vss vss vss vss vss vss vss vddi ab ac vddo vddo vddi vddi vddo vddo vddi vddi vss vddi ac ad vss nc8 vss vss vss vss vss vddi vss vss ad ae nc7 nc10 vddo vddo vddi vddi vss vddo vddo vss ae af nc9 vss vss vss vss vddi vss vss vddo vss af ag vddo vddo vddo vddo vss vddi vddi vss vddo vddo ag ah vss vss vss vddo vss vss vddi vss vss vddo ah aj vddi vddi vss vddo vddo vss vddo vddo vss vddi aj ak vddi vss vss vddo vss vss vddo vss vddi ak 30 29 28 27 26 25 24 23 22 21
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 29 document no.: pmc-2001304, issue 7 figure 6 ball view 2 20 19 18 17 16 15 14 13 12 11 a dtrb rstb vddi vss vddo vddo vss vddi d[5] d[9] a b tdat_p[15] tsclk a[1] vss vddi vddo vss a[10] d[1] d[3] b c tdat_n[13] tctl_n csb a[9] vddi vddi a[11] d[2] d[6] d[4] c d vss tdat_p[13] tctl_p a[3] a[0] a[5] a[7] d[0] ale vss d e vss vddo intb tstat[1] a[2] a[14] a[6] a[12] vddo vss e f tdat_p[11] vddo vss wrb tstat[0] a[4] a[8] vss vddo d[15] f g vss vss vss vddo rdb a[13] vddo vss d[8] mdc g h tdat_p[7] vss vss vddo vss vss vddo d[11] mdio nc4 h j vddi vddi vddo vddo vss vss vddo vddo vddi vddi j k vss vddi vddi vddo vddo vddo vddo vddi vddi vss k l vss vddi vddi vddi vddo vddo vddi vddi vddi vss l m vddi vddi vss vddi vddi vddi vddi vss vddi vddi m n vddi vss vss vddi vddi vddi vddi vss vss vddi n p vddi vddi vddi vddi vss vss vddi vddi vddi vddi p r vddo vddi vddi vss vss vss vss vddi vddi vddo r t vddo vddi vddi vss vss vss vss vddi vddi vddo t u vddi vddi vddi vddi vss vss vddi vddi vddi vddi u v vddi vss vss vddi vddi vddi vddi vss vss vddi v w vddi vddi vss vddi vddi vddi vddi vss vddi vddi w y vss vddi vddi vddi vddo vddo vddi vddi vddi vss y aa vss vddi vddi vddo vddo vddo vddo vddi vddi vss aa ab vddi vddi vddo vddo vss vss vddo vddo vddi vddi ab ac vddi vddi vddo vddo vss vss vddo vddo vddi vddi ac ad vddi vss vss vddo vddi vddi vddo vss vss vddi ad ae vddo vddo vss vddi vss vss vddi vss vddo vddo ae af vss vddo vss vddi vddi vddi vddi vss vddo vss af ag vss vddo vss vss vss vss vss vss vddo vss ag ah vss vddo vddo vddo vddi vddi vddi vddo vddo vss ah aj vss vss vss vss vddo vddi vss vss vss vss aj ak vddi vddi vddi vss vddo vddo vss vddi vddi vddi ak 20 19 18 17 16 15 14 13 12 11 figure 7 ball view 3 10 9 8 7 6 5 4 3 2 1 a d[7] d[13] vddo vss tms vclk4 rx_los phase_init vddi a b d[10] vss vddo trstb vclk3 vclk_forceb sync_err vss vddi vddi b c vddo vss tdi d[12] vclk5 rx_sysclk2 vddo vss vss txdata4_p[3] c d vddo tck vclk1 vclk6 tx_sysclk2 vss vddo vddo txdata4_n[3] txdata4_p[1] d
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 30 document no.: pmc-2001304, issue 7 e tdo nc3 nc1 cpref_clk vddi vss vss oifs_res txdata4_n[1] txdata3_p[2] e f vclk2 nc2 nc11 vss vddi vddi oifs_resk txclk4_p txdata3_n[2] txclk_src4_n f g d[14] paused vddi vss vss txdata4_p[2] txclk4_n tx data4_p[0] txclk_src4_p vss g h phase_err vss vddi vddi txdata4_n[2] vss txdata4_n[0] txclk2_p vddo vddo h j vddi vss vss vss vss txdata3_p[3] txclk2_n vss vss txclk3_p j k vddi vddi vss avdhvref txdata3_n[3] txdata3_p[1] vddo vddo txclk3_n txdata3_p[0] k l vss vddi vss vss txdata3_n[1] vss vss txclk_src3_n txdata3_n[0] txdata2_p[3] l m vddi vddi vss vss vddo vddo txclk_src3_p txdata2_p[2] tx data2_n[3] txclk_src2_n m n vddi vddo vss vss vss txclk1_p txdata2_n[2] tx data2_p[1] txclk_src2_p vddi n p vddo vddo vddo vddo txclk1_n txdata2_p[0] txdata2_n[1] txdata1_p[3] vss vss p r vddo vss vss vss txdata2_n[0] txclk_src1_p txdata1_n[3] vddi vddi vddo r t vddo vss vss vss txdata1_n[2] txclk_src1_n txdata1_n[1] vddi vddo vddo t u vddo vddo vddo vddo txdata1_n[0] txdata1_p[2] oifs_atb[1] txdata1_p[1] vss vss u v vddi vddo rxdata3_p[0] vss vss txdata1_p[0] rxdata4_p[1] oifs_atb[0] rxdata4_p[3] vddi v w vddi vddi rxdata3_p[1] rxdata3_n[0] vddo vddo rxdata3_p[3] rxdata4_n[1] rxdata4_p[0] rxdata4_n[3] w y vss vddi vss rxdata3_n[1] rxdata3_p[2] vss vss rxdata3_n[3] rxdata4_p[2] rxdata4_n[0] y aa vddi vddi vss vss rxclk3_p rxdata3_n[2] vddo vddo rxclk4_p rxdata4_n[2] aa ab vddi vss vss vss rxdata2_p[1] rxclk3_n rxclk2_p vss vss rxclk4_n ab ac vddi vss vddi vddi rxdata1_p[0] rxdata2_n[1] rxdata2_p[2] rxclk2_n vddo vddo ac ad vss vss vddi vss vss rxdata1_n[0] rxclk1_p rxdata2_n[2] rxdata2_p[3] vss ad ae vss vddo vddo vss vddi vddi rxdata1_p[2] rxclk1_n rxdata2_p[0] rxdata2_n[3] ae af vss vddo vss vss vddi vss vss rxdata1_n[2] rxdata1_p[3] rxdata2_n[0] af ag vddo vddo vss vddi vddi vss vddo vddo rxdata1_p[1] rxdata1_n[3] ag ah vddo vss vss vddi vss vss vddo vss vss rxdata1_n[1] ah aj vddi vss vddo vddo vss vddo vddo vss vddi vddi aj ak vddi vss vddo vss vss vddo vss vss vddi ak
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 31 document no.: pmc-2001304, issue 7 9 pin description table 2 s/uni-1x10ge line side signaling interface pin name type pin no. function rxclk2+ rxclk2- analog lvds input ab4 ac3 receive clock 2 rxclk2 is 644.53125mhz clock. rxclk2 is used to sample the 16 receive data steams at rising edge. the rxclk2 pins correspond to pma_rx_clk +/- in the ieee 802.3ae standard rxclk4+ rxclk4- rxclk3+ rxclk3- rxclk1+ rxclk1- analog lvds input aa2 ab1 aa6 ab5 ad4 ae3 receive clock [4, 3, 1] unused the unused rxclk[4,3,1] inputs need to have the neg (-) pins tied to 3.3v through a 4.7k ohm resistor. the pos (+) pins must be tied to ground through a zero ohm resistor. rxdata1[0]+ rxdata1[0]- rxdata1[1]+ rxdata1[1]- rxdata1[2]+ rxdata1[2]- rxdata1[3]+ rxdata1[3]- rxdata2[0]+ rxdata2[0]- rxdata2[1]+ rxdata2[1]- rxdata2[2]+ rxdata2[2]- rxdata2[3]+ rxdata2[3]- rxdata3[0]+ rxdata3[0]- rxdata3[1]+ rxdata3[1]- rxdata3[2]+ rxdata3[2]- rxdata3[3]+ rxdata3[3]- rxdata4[0]+ rxdata4[0]- rxdata4[1]+ rxdata4[1]- rxdata4[2]+ rxdata4[2]- rxdata4[3]+ rxdata4[3]- analog lvds input ac6 ad5 ag2 ah1 ae4 af3 af2 ag1 ae2 af1 ab6 ac5 ac4 ad3 ad2 ae1 v8 w7 w8 y7 y6 aa5 w4 y3 w2 y1 v4 w3 y2 aa1 v2 w1 the differential receive data (rxdata) inputs carry the byte-serial 10gigabit ethernet stream. pin rxdata1[0] corresponds to rx_data_unit<0> while rxdata4[3] corresponds to rx_data_unit<15> as described in figure 49-2 of ieee802.3ae standard.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 32 document no.: pmc-2001304, issue 7 pin name type pin no. function txclk_src2+ txclk_src2- analog lvds input n2 m1 transmit source clock txclk_src2 is a 644.53125mhz reference clock from serdes. all 16 transmit data streams txdatai_j (i=1 to 4 & j=1 to 4) are transmitted with reference to txclk_src2. the txclk_src2 pins correspond to pma_txclk_src +/- in the ieee 802.3ae standard. txclk_src4+ txclk_src4- txclk_src3+ txclk_src3- txclk_src1+ txclk_src1- analog lvds input g2 f1 m4 l3 r5 t5 transmit source clock txclk_src[4, 3, 1] unused the unused txclk_src[4,3,1] inputs need to have the neg (-) pins tied to 3.3v through a 4.7k ohm resistor. the pos (+) pins must be tied to ground through a zero ohm resistor. txclk2+ txclk2- analog lvds output h3 j4 transmit clock txclk2 is a 644.53125mhz clock to synchronize the transmission of the 16 transmit data streams. the txclk2 pins correspond to pma_tx_clk +/- in the ieee 802.3ae standard. the txclk2+/- lvds outputs are internally terminated by the pm3392. txclk4+ txclk4- txclk3+ txclk3- txclk1+ txclk1- analog lvds output f3 g4 j1 k2 n5 p6 transmit clock txclk[4,3,1] are unused. the txclk2+/- lvds outputs are internally terminated by the pm3392.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 33 document no.: pmc-2001304, issue 7 pin name type pin no. function txdata1[0]+ txdata1[0]- txdata1[1]+ txdata1[1]- txdata1[2]+ txdata1[2]- txdata1[3]+ txdata1[3]- txdata2[0]+ txdata2[0]- txdata2[1]+ txdata2[1]- txdata2[2]+ txdata2[2]- txdata2[3]+ txdata2[3]- txdata3[0]+ txdata3[0]- txdata3[1]+ txdata3[1]- txdata3[2]+ txdata3[2]- txdata3[3]+ txdata3[3]- txdata4[0]+ txdata4[0]- txdata4[1]+ txdata4[1]- txdata4[2]+ txdata4[2]- txdata4[3]+ txdata4[3]- analog lvds output v5 u6 u3 t4 u5 t6 p3 r4 p5 r6 n3 p4 m3 n4 l1 m2 k1 l2 k5 l6 e1 f2 j5 k6 g3 h4 d1 e2 g5 h6 c1 d2 the differential transmit data (txdata) outputs carries the byte-serial 10gigabit ethernet stream. pin txdata1[0] corresponds to tx_data_unit<0> while txdata4[3] corresponds to tx_data_unit<15> as described in figure 49-2 of ieee802.3ae standard the txdata+/- lvds outputs are internally terminated by the pm3392. phase_err input cmos h10 the phase error (phase_err) input indicates when the txclk2+/- output is not aligned with the corresponding txdata+/- bus. when asserted, the receiving line side device cannot use the source synchronous txclk2 to sample the txdata bus. phase_err is treated as an asynchronous signal and is used to trigger maskable interrupt. in addition, the associated phase_init output shou ld be asserted to reinitiate alignment under user control. sync_err input cmos tri-state b4 the synchronization error (sync_err) input indicates that rxdata bus can be safely sampled. when sync_err is high, rxdata+/- is not derived from the optical line and is suspect. when sync_err is low, rxdata is recovered from the optical stream. the sync_err signal is treated as an asynchronous input.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 34 document no.: pmc-2001304, issue 7 pin name type pin no. function phase_init output cmos tri-state a3 the phase initialization (phase_init) output indicates to the receiving device that the device should start the txclk[2]+/- and txdata[n]+/- alignment process. the phase_init output is driven by a top level register programmed by software. pause input cmos internal pull down aa29 the pause (pause) signal is controlled by the system level interface to request the internal transmit mac to send pause frames through the line side to initiate flow control. pause frames are sent at a prescribed interval programmed in the pause timer register. pause is active high and is treated as an asynchronous input. paused output cmos tri-state g9 the paused (paused) signal is controlled by the transmit mac to indicate the mac is currently acting upon an ingressed pause frame as indicated from the receive mac. paused is active high and is treated as an asynchronous output. table 3 s/uni-1x10ge system side signaling interface pin name type pin no. function refsel[1] refsel[0] input cmos schmitt trigger internal pull up u26 t25 the pos-phy level 4 reference clock select determines the source and frequency of the reference clock used to generate the internal clocks for the pl4 bus interface logic on the pm3392. when refsel[0] is low the reference clock is derived from tdclk+/- (slave mode). when refsel[0] is high the reference clock is derived from refclk+/- (master mode). when refsel[1] is low in slave mode the train_dis and odat_dis bits in the pl4io configuration register ar e initially cleared and tdclk+/- must be valid before de-asserting rstb. when refsel[1] is high in slave mode the train_dis and odat_dis bits in the pl4io configuration register are initially set and tdclk+/- must be valid before these bits are cleared. when refsel[1] is low in master mode the selected pm3392 internal pl4 reference clock frequency is ? the pl4 data rate. when refsel[1] is high in master mode the selected reference clock frequency is ? the pl4 data rate. refsel should only be switched while rstb is asserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 35 document no.: pmc-2001304, issue 7 pin name type pin no. function pl4_rclk+ pl4_rclk- differential pecl input g26 h25 the pos-phy level 4 reference is an optional 155.5 mhz to 350 mhz, 40-60% duty cycle clock reference which is used to generate rdclk+/- and provide phase references for tdat[15:0]+/- de-skewing. pl4_rclk is ignored when refsel[0] is logic 0 (slave mode) and used when refsel[0] is logic 1 (master mode). the actual frequency of pl4_rclk in master mode must be between 311.0 mhz and 350 mhz when refsel[1] is low and is frequency locked to tdclk+/-. the actual frequency of pl4_rclk in master mode must be between 155.5 mhz and 175 mhz when refsel[1] is high and is frequency locked to tdclk+/- divided by 2. pl4_rclk+/- should be stable before de- asserting rstb if refsel[0] is a logic 1 (master mode). if the pos-phy level 4 reference clock is used, it is recommended to use pl4_rclk as a differential pecl input. the pl4_rclk+/- pecl inputs are not internally terminated by the pm3392. rdclk+ rdclk- analog lvds output m28 n27 the pos-phy differential receive clock (rdclk+/-) is a 1*pl4_rclk, 2*pl4_rclk or tdclk mhz, 45-55% duty cycle source synchronous clock. when operating in pl4 master mode, rdclk+/- is a 1x or 2x multiplied version of the pl4_rclk+/- inputs. when operating in pl4 slave mode, rdclk+/- is a loop-timed version of tdclk+/-. rdclk+/- is provided to downstream devices to clock in rdat[15:0]+/- and rctl+/-. the rising and falling edges of rdclk+/- are used to update rdat[15:0]+/- and rctl+/-. the rdclk+/- lvds outputs are internally terminated by the pm3392.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 36 document no.: pmc-2001304, issue 7 pin name type pin no. function rdat[15]+ rdat[15]- rdat[14]+ rdat[14]- rdat[13]+ rdat[13]- rdat[12]+ rdat[12]- rdat[11]+ rdat[11]- rdat[10]+ rdat[10]- rdat[9]+ rdat[9]- rdat[8]+ rdat[8]- rdat[7]+ rdat[7]- rdat[6]+ rdat[6]- rdat[5]+ rdat[5]- rdat[4]+ rdat[4]- rdat[3]+ rdat[3]- rdat[2]+ rdat[2]- rdat[1]+ rdat[1]- rdat[0]+ rdat[0]- analog lvds output y30 w29 v28 u27 u28 t27 w30 v29 p26 r25 p28 r27 n28 p27 m30 n29 l30 m29 k30 l29 n26 p25 l28 m27 j30 k29 k26 l25 h28 j27 f30 g29 the pl4 differential receive data (rdat[15:0]+/-) bus carries the ethernet frame data that are read from the ingress fifo and the in-band control words which describes the stream. in-band control words are identified using the rctl+/- output. please refer to the operations section for a description of the pos- phy level 4 protocol and the bus data structures. rdat[15:0]+/- is updat ed on both edges of rdclk+/-. the rdat[15:0]+/- lvds outputs are internally terminated by the pm3392. rctl+ rctl- analog lvds output aa30 y29 the pl4 differential receive control (rctl+/- ) signals identify control words on the rdat[15:0]+/- bus. when rctl+/- is high, a control word is on the rdat[15:0]+/- bus. if rctl+/- is low, a payload word is on the rdat[15:0]+/- bus. rctl+/- is updated on both edges of rdclk+/-. the rctl+/- lvds outputs are internally terminated by the pm3392.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 37 document no.: pmc-2001304, issue 7 pin name type pin no. function rsclk input 3v cmos schmitt trigger ab30 the pl4 receive status clock (rsclk) is the optional fifo status input clock supplied by the peer pl4 device and is used to transfer fifo status from the peer pl4 device to another device. the actual frequency of rsclk is determined by the peer device. the maximum frequency of rsclk is at 1/8 of the pl4 data transfer rate (rdclk/4 mhz). conforming to the pl4 bus specification requirement that implem entation of the fifo status channel in the receive interface is optional, rsclk may be tied to a logic 0 if the receive status bus is not used. refer to the operations section for additional details (subsection operation with pl4 receive fifo status unimplemented). rstat[1] rstat[0] input cmos w27 y28 the pl4 receive status (rstat[1:0]) bus is used to indicate the status of the downstream device?s fifo. for the fifo, a satisfied, hungry or starving condition can be indicated. in addition, a special two-bit code is used for framing and alignment. please refer to the operation section for the status definitions and the status protocol. rstat[1:0] is sampled on the rising edge of rsclk. conforming to the pl4 bus specification requirement that implem entation of the fifo status channel in the receive interface is optional, rstat may be tied to a logic 0 if the receive status bus is not used. refer to the operations section for additional details (subsection operation with pl4 receive fifo status unimplemented). tdclk+ tdclk- analog lvds input b25 a26 the pl4 differential transmit clock (tdclk+/-) is a 311 mhz to 350 mhz, 45-55% duty cycle source synchronous clock. tdclk+/- is used to clock the transmit pos-phy circuitry when in slave mode. when configured for pl4 master mode, tdclk+/- must be frequency locked to the pl4_rclk+/-. lvds inputs are internally terminated to 100- ohm differential impedance.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 38 document no.: pmc-2001304, issue 7 pin name type pin no. function tdat[15]+ tdat[15]- tdat[14]+ tdat[14]- tdat[13]+ tdat[13]- tdat[12]+ tdat[12]- tdat[11]+ tdat[11]- tdat[10]+ tdat[10]- tdat[9]+ tdat[9]- tdat[8]+ tdat[8]- tdat[7]+ tdat[7]- tdat[6]+ tdat[6]- tdat[5]+ tdat[5]- tdat[4]+ tdat[4]- tdat[3]+ tdat[3]- tdat[2]+ tdat[2]- tdat[1]+ tdat[1]- tdat[0]+ tdat[0]- analog lvds input b20 a21 b21 a22 d19 c20 d22 c23 f20 e21 f21 e22 b24 a25 d23 c24 h20 g21 f22 e23 d24 c25 b26 a27 f23 e24 h21 g22 b27 a28 d25 c26 the pl4 differential transmit data (tdat[15:0]+/-) bus carries ethernet frame data that are written into the egress fifo and the in- band control words which describes the stream. in-band control words are identified using the tctl+/- input. please refer to the operations section for a description of the pos-phy level 4 protocol and the bus data structures. tdat[15:0]+/- is sampled on both edges of tdclk+/-. tctl+ tctl- analog lvds input d18 c19 the pl4 differential transmit control (tctl+/-) signals identify control words on the tdat[15:0]+/- bus. when tctl+/- is high, a control word is on the tdat[15:0]+/- bus. if tctl+/- is low, a payload word is on the tdat[15:0]+/- bus. tctl+/- is sampled on both edges of tdclk+/-. tstat[1] tstat[0] output cmos tri-state e17 f16 the pl4 transmit status (tstat[1:0]) bus is used to indicate the stat us of the s/uni-1x10ge egress fifos. a satisfied, hungry or starving condition can be indicated. please refer to the operation section for the status definitions and the status protocol. tstat[1:0] is updated on the rising edge of tsclk.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 39 document no.: pmc-2001304, issue 7 pin name type pin no. function tsclk output cmos tri-state b19 the pl4 transmit status clock (tsclk) is a tdclk/4 mhz, 40/60% duty cycle source synchronous clock. tsclk is used to clock the transmit status circuitry. the rising edge of tsclk is used to update tstat[1:0]. table 4 ecbi signals and mdc/mdio pin name type pin no. function csb input cmos c18 the active low chip select (csb) signal is low during s/uni-1x10g e register accesses. if csb is not required (i.e. register accesses controlled using the rdb and wrb signals only), csb must be connected to an inverted version of the rstb input. rdb input cmos g16 the active low read enable (rdb) signal is low during a s/uni-1x10ge read access. the s/uni-1x10ge driv es the d[15:0] bus with the contents of the addressed register while rdb and csb are low. wrb input cmos f17 the active low write strobe (wrb) signal is low during a s/uni-1x10ge register write access. the d[15:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] bi-directional cmos f11 g10 a9 c7 h13 b10 a11 g12 a10 c12 a12 c11 b11 c13 b12 d13 the bi-directional data bus (d[15:0]) is used during s/uni-1x10ge read and write accesses. a[14] (trs) input cmos e15 the test register select (trs) signal selects between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. trs may be tied low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 40 document no.: pmc-2001304, issue 7 pin name type pin no. function a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] input cmos g15 e13 c14 b13 c17 f14 d14 e14 d15 f15 d17 e16 b18 d16 the address (a[13:0]) bus selects specific registers during s/uni-1x10ge register accesses. rstb input cmos schmitt trigger internal pull up a19 the active low reset (rstb) signal provides an asynchronous s/uni-1x10ge reset. rstb is a schmitt triggered input with an integral pull-up resistor. ale input cmos internal pull up d12 the address latch enable (ale) is an active-high signal and latches the address bus a[13:0] when low. when ale is high, the internal address latches are transparent. it allows the s/uni-1x10ge to interface to a multiplexed address/data bus. the ale input has an integral pull up resistor. intb output cmos tri-state e18 the active low interrupt (intb) is set low when an s/uni-1x10ge enabled interrupt source is active. the s/uni-1x10ge may be enabled to report many alarms or events via interrupts. intb is tri-stated when the interrupt is acknowledged via the appropriate register access. intb is an open drain output. mdc output cmos tri-state g11 management data clock (mdc) output signal is approximately 2.5mhz with a 50% duty cycle clock for the mdio. mdio bi-directional cmos internal pull down h12 management data io (mdio), is a bi- directional signal that send and receives status data from an external mii phy. the output management frame bit serial signal is updated on the rising edge of mdc. input bit serial status data is sampled on the rising edge of mdc. mdio has an internal pull down resistor.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 41 document no.: pmc-2001304, issue 7 table 5 jtag and reserved signals pin name type pin no. function tck input schmitt trigger cmos internal pull up d9 the test clock (tck) signal provides timing for test operations that can be carried out using the ieee p 1149.1 test access port. tck has an integral pull up resistor. tms input schmitt trigger cmos internal pull up a6 the test mode select (tms) signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor. tdi input schmitt trigger cmos internal pull up c8 when the s/uni-1x10ge is configured for jtag operation, the test data input (tdi) signal carries test data into the s/uni-1x10ge via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor. tdo output cmos tri-state e10 the test data output (tdo) signal carries test data out of the s/uni-1x10ge via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is inactive except when scanning of data is in progress. trstb input schmitt trigger cmos internal pull up b7 the active low test reset (trstb) signal provides an asynchronous s/uni-1x10ge test access port reset via the ieee p1149.1 test access port. trstb is a schmidt triggered input with an integral pull up resistor. in the event that trstb is not used, it must be connected to rstb.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 42 document no.: pmc-2001304, issue 7 pin name type pin no. function dtrb input schmitt trigger cmos internal pull down a20 digital-core timer reset bypass (dtrb ) is used to override the internal digital-core timer reset signal from the pl4 sub-system. the timer reset allows the analog circuitry (specifically clock recovery or generation) to stabilize before the digital-core logic is release from the reset state for a more controlled initialization. dtrb is logically ored to the internal digital-core timer reset signal. dtrb must be asserted when rstb is asserted. when rstb is de-asserted, dtrb can then be de- asserted with a delay of up to 10ms. when dtrb is de-asserted before the internal timer reset expires, t he digital-core timer reset is overridden by dtrb. dtrb is reserved for pmc test purposes only. dtrb is a schmitt trigger input with an internal pull down. it is required that this pin be strapped low for normal operation. cpref_clk input schmitt trigger cmos e7 chopper reference clock, cpref_clk , is a 60-81mhz clock with a 40/60 duty cycle or better, input that must be stable before the deassertion of pin reset. vclk1 vclk2 vclk3 vclk4 vclk5 vclk6 input mos d8 f10 b6 a5 c6 d7 vclk[n] is reserved for pmc test purposes. vclk[n] must be strapped low for normal operation. vclk_forceb input cmos b5 vclk_forceb is used in conjunction with vclk[n]. vclk_forceb is reserved for pmc test purposes only and must be strapped high for normal operation. tx_sysclk2 output mos tri-state d6 tx_sysclk2 is used for diagnostic purpose only, these should be left as no connects externally. rx_sysclk2 output mos tri-state c5 rx_sysclk2 is used for diagnostic purpose only, these should be left as no connects externally. rx_los output mos tri-state a4 rx_los is used for diagnostic purpose only, these should be left as no connects externally.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 43 document no.: pmc-2001304, issue 7 pin name type pin no. function nc1 nc2 nc3 nc4 nc5 nc6 nc7 nc8 nc9 nc10 nc11 input mos internal pull up e8 f9 e9 h11 v27 w28 ae30 ad29 af30 ae29 f8 reserved, nc1-11 are no connects externally. table 6 s/uni-1x10ge analog pins pin name type pin no. function pl4_res pl4_resk differential analog bi- directional f29 e30 pl4 reference resistor connection . an off-chip 3.16k 1% resistor is connected between the positive resistor reference pin pl4_res and a kelvin ground contact pl4_resk for the txlvref circuitry. an on-chip negative feedback path will force an internal 0.80v reference voltage onto pl4_res, therefore forcing 252 a of current to flow through the resistor. this current is used by the transmitter blocks. pl4_avdh[3] pl4_avdh[2] pl4_avdh[1] pl4_avdh[0] analog power j26 c30 d29 f27 the pl4 analog power high (pl4_avdh[0:3]) pins for the pl4 interface analog circuits. the pl4_avdh[0:3] pins should be connected through passive filtering networks to a well decoupled +3.3v analog power supply. see operation section for detailed information. pl4_avdl[3] pl4_avdl[2] pl4_avdl[1] analog power e28 f28 g27 the pl4 analog power low (pl4_avdl[1:3]) pins for the pl4 interface analog circuits. pl4_avdl[1:3] pins should be connected through passive filtering networks to a well decoupled +1.8v analog power supply. see operation section for detailed information. pl4_atb[5] pl4_atb[4] pl4_atb[3] pl4_atb[2] pl4_atb[1] pl4_atb[0] analog bi- directional h26 j25 d30 h27 e29 g28 the pl4 analog test pins (pl4_atb[5:0] are provided for production testing only. these pins must be tied to analog ground (vss) during normal operation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 44 document no.: pmc-2001304, issue 7 pin name type pin no. function oifs_res oifs_resk differential analog bi- directional e3 f4 oifs reference resistor connection . an off-chip 3.16k 1% resistor is connected between the positive resistor reference pin oifs_res and a kelvin ground contact oifs_resk for the txlvref circuitry. an on-chip negative feedback path will force an internal 0.80v reference voltage onto oifs_res, therefore forcing 252 a of current to flow through the resistor. this current is used by the transmitter blocks. avdhvref analog reference k7 avdhvref is the quiet txlvref analog power (avdhvref) is a +3.3v power supply for the quiet ana log blocks. this pin is de-coupled to vss via an on-chip capacitor and is also de-coupled externally to ground via a 0.1uf ceramic de- coupling capacitor for proper hf noise shunting. oifs_atb[1] oifs_atb[0] analog bi- directional u4 v3 the oifs analog test pins (oifs_atb[1:0] are provided for production testing only. these pins must be tied to analog ground (vss) during normal operation. table 7 digital power and ground pin name pin type pin no. function vddo digital i/o power a15 a16 a23 a8 aa14 aa15 aa16 aa17 aa23 aa24 aa27 aa28 aa3 aa4 ab13 ab14 ab17 ab18 ac1 ac13 ac14 ac17 ac18 ac2 the digital i/o power (vddo) pins should be connected to a well-decoupled +3.3v digital power supply.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 45 document no.: pmc-2001304, issue 7 pin name pin type pin no. function ac25 ac26 ac29 ac30 ad14 ad17 ae11 ae12 ae19 ae20 ae22 ae23 ae27 ae28 ae8 ae9 af12 af19 af22 af9 ag10 ag12 ag19 ag21 ag22 ag27 ag28 ag29 ag3 ag30 ag4 ag9 ah10 ah12 ah13 ah17 ah18 ah19 ah21 ah27 ah4 aj16 aj23 aj24 aj26 aj27 aj4 aj5 aj7 aj8 ak15 ak16 ak23 ak26 ak5 ak8
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 46 document no.: pmc-2001304, issue 7 pin name pin type pin no. function b15 b23 b8 c10 c21 c27 c4 d10 d21 d27 d28 d3 d4 e12 e19 f12 f19 g14 g17 h1 h14 h17 h2 h29 h30 j13 j14 j17 j18 k14 k15 k16 k17 k23 k24 k27 k28 k3 k4 l15 l16 m25 m26 m5 m6 n22 n9 p10 p21 p22 p23 p24 p7 p8 p9 r1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 47 document no.: pmc-2001304, issue 7 pin name pin type pin no. function r10 r11 r20 r21 r29 r30 t1 t10 t11 t2 t20 t21 t30 u10 u21 u22 u23 u24 u7 u8 u9 v22 v9 w25 w26 w5 w6 y15 y16 vddi digital core power a13 a18 a2 a29 aa10 aa12 aa13 aa18 aa19 aa21 aa22 aa25 aa26 aa9 ab10 ab11 ab12 ab19 ab20 ab21 ac10 ac11 ac12 ac19 ac20 ac21 ac23 the digital core power (vddi) pins should be connected to a well-decoupled +1.8v digital power supply.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 48 document no.: pmc-2001304, issue 7 pin name pin type pin no. function ac24 ac27 ac28 ac7 ac8 ad11 ad15 ad16 ad20 ad23 ad8 ae14 ae17 ae25 ae26 ae5 ae6 af14 af15 af16 af17 af25 af6 ag24 ag25 ag6 ag7 ah14 ah15 ah16 ah24 ah7 aj1 aj10 aj15 aj2 aj21 aj29 aj30 ak10 ak11 ak12 ak13 ak18 ak19 ak2 ak20 ak21 ak29 b1 b16 b2 b29 b30 c15 c16
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 49 document no.: pmc-2001304, issue 7 pin name pin type pin no. function e25 e6 f25 f26 f5 f6 g23 g8 h23 h24 h7 h8 j10 j11 j12 j19 j20 j21 k10 k12 k13 k18 k19 k21 k22 k9 l12 l13 l14 l17 l18 l19 l22 l9 m10 m11 m12 m14 m15 m16 m17 m19 m20 m21 m22 m23 m24 m9 n1 n10 n11 n14 n15 n16 n17 n20
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 50 document no.: pmc-2001304, issue 7 pin name pin type pin no. function n21 n30 p11 p12 p13 p14 p17 p18 p19 p20 r12 r13 r18 r19 r2 r28 r3 t12 t13 t18 t19 t28 t29 t3 u11 u12 u13 u14 u17 u18 u19 u20 v1 v10 v11 v14 v15 v16 v17 v20 v21 v30 w10 w11 w12 w14 w15 w16 w17 w19 w20 w21 w22 w23 w24 w9
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 51 document no.: pmc-2001304, issue 7 pin name pin type pin no. function y12 y13 y14 y17 y18 y19 y22 y9 vss digital / analog ground a14 a17 a24 a7 aa11 aa20 aa7 aa8 ab15 ab16 ab2 ab22 ab23 ab24 ab25 ab26 ab27 ab28 ab29 ab3 ab7 ab8 ab9 ac15 ac16 ac22 ac9 ad1 ad10 ad12 ad13 ad18 ad19 ad21 ad22 ad24 ad25 ad26 ad27 ad28 ad30 ad6 ad7 ad9 ae10 ae13 ae15 ae16 the digital/analog ground (vss) pins should be connected to the common digital/analog ground of the device power supply.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 52 document no.: pmc-2001304, issue 7 pin name pin type pin no. function ae18 ae21 ae24 ae7 af10 af11 af13 af18 af20 af21 af23 af24 af26 af27 af28 af29 af4 af5 af7 af8 ag11 ag13 ag14 ag15 ag16 ag17 ag18 ag20 ag23 ag26 ag5 ag8 ah11 ah2 ah20 ah22 ah23 ah25 ah26 ah28 ah29 ah3 ah30 ah5 ah6 ah8 ah9 aj11 aj12 aj13 aj14 aj17 aj18 aj19 aj20 aj22
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 53 document no.: pmc-2001304, issue 7 pin name pin type pin no. function aj25 aj28 aj3 aj6 aj9 ak14 ak17 ak22 ak24 ak25 ak27 ak28 ak3 ak4 ak6 ak7 ak9 b14 b17 b22 b28 b3 b9 c2 c22 c28 c29 c3 c9 d11 d20 d26 d5 e11 e20 e26 e27 e4 e5 f13 f18 f24 f7 g1 g13 g18 g19 g20 g24 g25 g30 g6 g7 h15 h16 h18
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 54 document no.: pmc-2001304, issue 7 pin name pin type pin no. function h19 h22 h5 h9 j15 j16 j2 j22 j23 j24 j28 j29 j3 j6 j7 j8 j9 k11 k20 k25 k8 l10 l11 l20 l21 l23 l24 l26. l27 l4 l5 l7 l8 m13 m18 m7 m8 n12 n13 n18 n19 n23 n24 n25 n6 n7 n8 p1 p15 p16 p2 p29 p30 r14 r15 r16
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 55 document no.: pmc-2001304, issue 7 pin name pin type pin no. function r17 r22 r23 r24 r26 r7 r8 r9 t14 t15 t16 t17 t22 t23 t24 t26 t7 t8 t9 u1 u15 u16 u2 u25 u29 u30 v12 v13 v18 v19 v23 v24 v25 v26 v6 v7 w13 w18 y10 y11 y20 y21 y23 y24 y25 y26 y27 y4 y5 y8 notes on pin description: 1. all s/uni-1x10ge inputs and bi-directional pins present minimum capacitive loading and operate at cmos/ttl logic levels except the lvds signals lis ted above in the pin description, which operate at lvds levels.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 56 document no.: pmc-2001304, issue 7 2. the s/uni-1x10ge digital outputs are 3.3v tolerant. 3. inputs ale, rstb, tms, tdi, tck and trstb have internal pull-up resistors. 4. the lvds inputs and outputs should be terminated in a passive network and interface at lvds levels as described in the operations section. 5. it is mandatory that every ground pin be connected to the printed circuit board ground plane to ensure reliable device operation. 6. it is mandatory that every power pin be connected to the printed circuit board power plane to ensure reliable device operation. 7. all analog power and ground pins can be sensitive to noise. they must be isolated from the digital power and ground. care must be taken to correctly decouple these pins. please refer to the xenon power supply filtering recommendati on application note. pmc-2010770. 8. due to esd protection structures in the pads, it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme c onditions it is possible to damage these esd protection devices or trigger latch up. please adhere to the recommended power supply sequencing as described in the operatio n section of this document. 9. do not exceed 100 ma of current on any signal pin during the power-up or power-down sequence. refer to the power sequ encing description in the operations section. 10. before any input activity occurs, ensure that the device power supplies are within their nominal voltage range. 11. hold the device in the reset condition until the dev ice power supplies are within their nominal voltage range.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 57 document no.: pmc-2001304, issue 7 10 functional description 10.1 primary interfaces, line side and system side 10.1.1 oifs and oifs digital wrapper, receive and transmit functionality the oifs performs the xsbi functionality as prescr ibed by 10 gigabit ieee 802.3ae standard compatible ethernet lan physical layer devices (lan phy). the block performs the conversion from channelized serial data to an internal parallel data stream for the ingress channel and also converts the internal parallel data stream to the resultant channelized serial bit stream for the egress channel. the oifs digital wrapper also supplies the loopback features for this device. both line side and system side loopback can be configured. all rele vant synchronization logic is contained in this block. 10.1.2 xsbi line interface the xsbi line interface block integrates analog block components (abc), along with supporting logic to implement a 16-bit interface (xsbi compliant) between the physical coding sub-layer (pcs) and the physical media device (pmd). on the receive direction, the xsbi reorders the sixteen 8-bit parallel data coming from the oifs (16 1:8 sipo which de-serializes a 644.53125 mbps bit serial data stream into an 80.63 mbps byte serial data stream) and provide a 128-bit sy stem side interface to the pcs sub-layer. the bit ordering (big-endian or little-endian ) within each 16-bit is programmable. on the transmit direction, the xsbi line interface takes a 128-bits of line data input from the pcs sub-layer and reorders it into sixteen 8-bit data to be provided to the sixteen 8:1 piso (each piso converts an 80.63 mbps byte serial data stream into a 644. 53125 mbps bit serial data stream). the interface also provides prbs (pseudo random bit sequencing) testing capability for the receive and transmit blocks within the xsbi. when in test mode on the receive side it monitors the incoming data sequence for errors, and on the transmit side it sends a pseudo random bit sequence. for the xsbi, there is no differen ce in operation between test mode and normal operation. 10.2 receive channel (ingress) ? line side to system side 10.2.1 receive 10g ethernet 64b/66b processor: r64b66b the receive 64b/66b processor implements all the required functionalit y of the 10 gigabit ethernet pcs interface as specified in the ieee 802.3ae standard. the r64b66b decoder performs 64b66b alignment, payload descram bling, 64b66b data/control decoding, and ethernet frame delineation. the resulting decoded st ream is then passed to the upstream device. the r64b66b implements the following principal functions:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 58 document no.: pmc-2001304, issue 7 ? ethernet frame delineation ? aligns to 32-bit sop boundaries ? 33:32 rate adaptation ? 64b66b data decoding ? 64b66b control code decoding ? data de-scrambling ? receive link fault signaling ? receive jitter test pattern checking rx pcs the rx pcs contains the finite state machin es for synchronization, receive data and bit error monitoring. it contains a de-scrambler based on g(x) = 1 + x 39 + x 58 . it provides all the timing and control necessary for capturing, aligni ng, and processing the downstream data. the decision(s) to leave or remain in a given st ate are based upon the ieee 802.3ae standard. the rx pcs provides jitter test pattern checking as per ieee 802.3ae standard. the receive sync state machine, shown in figure 10-1 below, contains four states pre- sync, hunt, sync and los and is based on th e synchronization process described in ieee 802.3ae standard clause 49. pre-sync is the start-up state, when in this state, it will attempt to sync on the incoming 2-bit sync field. if the 2-bit sync field is not a proper sync character of ?10? or ?01? then the state machine transiti ons to the hunt state. the hunt state will then shift the data by 2-bits. this shift will now provide the receive sync state machine with a new sync field and will attempt to synchroni ze on this new sync field. this process will continue until the current sync field and the next sync field are valid sync characters of ?10? or ?01?. when this happens the receive sync st ate machine monitors two counters, 64 block counter and 16 bad sync counter. the 64-block counter performs the 64-block window that is needed to maintain sync in the rx pcs, it c ounts 64 66-bit blocks and rolls over and starts again. the 16 bad sync counter is needed to c ount the number of bad sync fields received either ?11? or ?00?. if the receive sync state machine is seeing good sync and the 64 block counter = 64 and the 16 bad sync counter = 0, the state ma chine will transition to the sync state. when in the sync state the state mach ine continues to monitor the 64 block counter and the 16 bad sync counter, if the 16 bad sync counter is = 16 and the 64 block counter is less than 64 then the state machine transitions to the los state. the transition to the los state will cause the assertion of loss of sync and link fail status, which may cause an interrupt if enabled. loss of sync will cause the receive and ber state mach ines to transition to their init states. once in the los state the receive state machine, on the next clock cycle, transition to the hunt state to try and re-acquire sync.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 59 document no.: pmc-2001304, issue 7 figure 8 rx sync state machine counter16 >= 16 or sync_err = 1 power_on = true + reset sync_err = 1 sync_data = invalid pre-sync if else if else else if hunt if else sync if else los counter64 = 64 and counter16 = 0 the receive state machine, shown in figure 9 below, contains six states rx_init, rx_ctrl, rx_start, rx_data, rx_end, rx_err and is based on the receive state machine process described in ieee 802.3ae standard clause 49. the rx_init state is the start-up state and will not transition out of this state until th e receive sync state machine is in the sync state. when the receive state m achine is in the rx_init state no data will be transferred to the mac. once the receive sync state machine is in the sync state the receive state machine will monitor the sync and type fields of the incoming data stream to decide on the proper transitions between states.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 60 document no.: pmc-2001304, issue 7 figure 9 receive state machine power_on = true + reset sync = true sync = true and sop rx_init if else if else else if rx_ctrl rx_start rx_data sync = true and eop or data or err rx_end rx_err if else if else else if sop sync = false if else if else !data else if end and spkt_mode = true sync = false else if else if sync = false else if end eop or data or err err or ctrl or sop if else sync = false else if sop if else else if else if else if ctrl sync = false end sop or err
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 61 document no.: pmc-2001304, issue 7 the receive bit error rate (ber) state machine, shown in figure 10 below, contains six states rx_ber_init, rx_ber_test, rx_ber _bad, rx_ber_good, rx_hi_ber, rx_start_timer and is based on the receiv e ber state machine process described in ieee 802.3ae standard clause 49. the rx_ber_init state is the start-up state and will not transition out of this state until the receive sync state machine is in the sync state. no bit error monitoring will be performed when in th e rx_ber_init state. once the receive sync state machine is in the sync state the receive ber state machine will monitor the sync field of the incoming data stream to decide on the proper transitions between states. the receive ber state machine monitors two counters and the sync field of the incoming data stream. the two counters are a 125s counter and the high bit error counter. the 125s counter is an approximation based on the sys_clkx2 clock. th e sys_clkx2 period is ~6.2 ns, therefore the counter will count up to 20,162 clock periods and hold. the high bit error counter counts the number of invalid sync fields (?11? or ?00?).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 62 document no.: pmc-2001304, issue 7 figure 10 rx ber state machine power_on = true + reset sync = true rx_ber_init if else rx_ber_test rx_ber_bad rx_ber_good rx_hi_ber rx_start_timer if else if else else if sync = false if else else if else if sync = false else if sync = false if else sync = false else if if else sync = false sync_field = false sync_field = true and timer125_done = 1 else if sync_field = false and hi_ber_cnt < 15 timer125_done = 0 and hi_ber_cnt < 15 timer125_done = 1 and hi_ber_cnt < 16 timer125_done = 1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 63 document no.: pmc-2001304, issue 7 jitter test pattern checker the control detector can be put into a test mode (jitter test mode) where it counts errors in the received data. the other side of the link must be put into test mode, so that it is generating the expected data patterns. the jitter test pattern checker utilizes the lock state machine and the descrambler operating as they do during normal data reception. the hi_ber state machine is disabled during receive test pattern mode. when block_lock is true and the receive test pattern mode is active, the test pattern checker observes the output from the descr ambler. when the output of the descrambler is the data pattern or its inverse, a match is de tected. since the transmitter?s scrambler is loaded with a seed value every 128 blocks (block is 64 bits) and the receiver?s descrambler is running normally, a mismatch will be detected once ever y 128 blocks in the absence of errors. the transmitter reseeding the scrambler, and inverting the input data, causes this mismatch. the test pattern checker will count 128-block windows. the first mismatch in a window will not increment the test pattern error counter. any subsequent mismatch in a window indicates an error and will increment the j itter counter(register 0x2087). 10.2.2 receive 10g ethernet mac (rxxg) the receive 10g ethernet mac (rxxg) provides 10 gigabit media access control sub-layer processing on a single 10 gigabit ethernet stre am. the rxxg expects data from the r64b66b block. the exact data throughput is determined by the system clock frequency, the inter-packet or intra-packet gaps received from the line in terface, and the backpressure received from the fifo interface. the rxxg implements the following principal functions: ? ethernet framing (detection and framing to the standard preamble/sfd sequence, removal of the preamble/sfd, and checking of the 32- bit crc field) and frame validation (marking of errored frames for discard). ? frame timing check (relative to the receive input clock reference): the rxxg will verify that the interframe gap does not fall below a pre-set minimum, and will filter frames that violate this restriction, when used in lan-mode devices. ? optional received frame filtering: frames can be discarded if they are found to contain length or crc errors. the rxxg block impl ements a 2048-byte full-frame buffer to facilitate this filtering. note that jumbo frame s (>1522 bytes) will not be filtered, but will be marked for discard by a downstream entity. ? received frame stream parsing, and pause ma c control frame detection, validation and extraction. the pause timer fields of received pause frames are extracted and sent to flow control logic on a separate set of signals. ? receive statistics support: the rxxg checks ev ery received frame against the ieee 802.3 frame error criteria, and outputs a statistics vector at the end of every received frame. the statistics vector is expected to be used by an external unit to update the appropriate statistics counters, which should be used to implem ent the standard ethernet mibs for link management.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 64 document no.: pmc-2001304, issue 7 ? optional receive pad stripping for all non-errored packets received. the rxxg functional sub units include ? receive mac (rmac) framer ? crc checker ? receive mac (rmac) parser ? receive fifo rmac framer the rmac framer monitors for valid wo rds from the r64b66b block, expecting preambles/sfd bytes. if the framer is looking for standard ethernet preamble/ sfd, it can also be configured to validate the preamble byte cont ents and length. if errors are detected, rmac framer will discard the frame. if no errors are f ound, the preamble and sfd are stripped and the following frame byte marked as the mac header sop. at this stage, the rmac framer writes the frame into an internal fifo. the rmac parser starts mac frame parsing and the crc checker starts accumulation. purep, and longp are register configuration bits that are set in the rxxg configuration 1 register, address 0x2040 . the device defaults to purep disabled where only the sfd is evaluated. if purep is enabled, the device will ignore frames with anything other than 0x55 or pure preamble. table 8 preamble checking purep longp preamble/sfd framing accepted 0 0 1-11 bytes of non-0xd5 byte values followed by 0xd5 (sfd) byte 0 1 any number >1 byte of non-0xd5 byte values followed by 0xd5 (sfd) byte 1 0 1-11 bytes of 0x55 byte values followed by 0xd5 (sfd) byte 1 1 any number >1 byte of 0x55 byte values followed by 0xd5 (sfd) byte rmac framer maintains a packet count and will perform in-range checking for type-length field values between 0 and 1518 bytes. packet s with in-range errors may be optionally discarded. rmac framer verifies packet size against the minimum value (64 bytes) and maximum programmable frame size. packets outsi de this range may be optionally discarded. table 9 lists the range, packet size checks a nd resulting packet classification. all the actual length value checks must have rx_maxfr, maximum frame, and value incremented by 4 for the case where the packet is vlan tagged. also note that ?crc result? also takes into consideration the case where the packet eop received from the line had line_err set, and this case is treated as if the packet had a bad crc. table 9 range, size and crc result processing type/length field (tl) actual packet size crc r esult packet classification x < 64 good undersize
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 65 document no.: pmc-2001304, issue 7 type/length field (tl) actual packet size crc r esult packet classification x < 64 bad fragment x > rx_maxfr good frametoolong x > rx_maxfr bad jabber x >63 & <= rx_maxfr bad framewithfcserror 46 - 1500 tl + 18 good good 46 ? 1500 tl + 22 & (vlan tagged) good good 46 - 1500 !(tl+18) & (> 64 & <= rx_maxfr) good inrangelengtherror < 46 64 good good < 46 >63 & <= rx_maxfr good inrangelengtherror 1501-1536 - good good < 46 68 & (vlan tagged) good good < 46 >64 & <= rx_maxfr & !( 68 & vlan) good inrangelengtherror 1501-1536 - good good > 1536 > 64 & <= rx_maxfr good good once an eop is received from the r64b66b bl ock, the rmac framer waits for a crc result to be returned from the crc ch ecker and packet filter status from the rmac parser. it will then inform the fifo controller about fifo flushi ng of the packet or forwarding of the packet to the system interface. if the packet is termin ated with an error flag set with eop, rmac framer may discard the packet only if it is less than 1900 bytes in length. if the frame is larger than the internal ram capac ity, the frame will not be discarded on error, but marked appropriately and transmitted. the rmac framer can be configured to ch eck for a minimum inter-packet gap between received frames. if this is enabled, the rmac framer will ignore packets when the sop is received during the ipg. crc checker the crc checker performs a crc-32 calculation on the entire data frame received from the rmac framer. the 32-bit crc result is compared to a constant expected value and a good / bad crc status is returned to the rmac framer. rmac parser the rmac parser classifies the packet accordi ng to mac header fields, da, sa, type/length and optional vlan tag. if address filters have been enabled, the required address and optional vlan id are applied to an address filter function, which will determine if the packet should be forwarded or filtered. in add ition, if multicast hashing has been enabled, multicast das are applied to a crc-32 hash function, resulting in an index into a 64-bit mhash register and a filtering/ forwarding decision made. the address filter block resets to a promiscuous mode of operation, whereby all filtering is disabled.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 66 document no.: pmc-2001304, issue 7 the rmac parser checks for received pause contro l packets and, if enabled, will transfer the extracted pause parameter to the txxg. the rmac framer may be configured to forward or filter received mac control packets of all typ es. when the rmac parser updates the rmac framer with packet classification information (after eop), rmac framer will make a forward/filter decision. receive fifo the purpose of the fifo is to provide the cap ability to discard erred frames, up to a maximum size of 1522 bytes (maximum expected frame size). this fifo is independent of the ingress flexible fifo (iflx), which contains the main ingress system buffering. two modes of operation are provided: store forward and cut through. in store-and-forward mode, frame transfer to th e iflx only begins once the complete frame has been written to the fifo. this will not deal w ith a situation where an oversized frame is received. hence a fifo read threshold has been provided, which will be initialized to a value > maximum size frame divided by 8. this will ensu re that if the fifo fills beyond this level, the read port will begin transferring the frame to the iflx. the same fifo read threshold could be used to configure the fifo for a cut-through mode, with all error frame discard functions disabled. in this case, the iflx would be informed to begin frame transfer when a small number of entries have been written into the fifo. 10.2.3 ingress flexible fifo (iflx) the ingress flexible fifo (iflx) provides a fi fo to separate the line-side timing from the higher layer system timing and the associated pl4 system interface. the iflx receives line side data from the ten gigabit ethernet phys ical port via the xsbi interface, r64b66b and rxxg blocks. the iflx provides 128kb (131,072 bytes) of storage in total. the configuration of the buffer space cannot be done dynamically. changes to the buffer are to be done during device initialization. the fifo has a low watermar k, and a high watermark. the low and high watermarks can be used for ethern et pause flow control operation. when the iflx ingress fifo reaches the progra mmed high watermark flow control threshold the ingress fifo will assert an indication to the transmit mac (txxg) to start pause flow control. the iflx ingress fifo will continue to keep the flow control signal asserted until the number of entries in the fifo have decreased to the programmed low watermark flow control threshold level.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 67 document no.: pmc-2001304, issue 7 in the event that the pl4 system-side sink devi ce indicates that it is no longer able to accept ethernet frame data (so pl4 fifo status fro m the system-side sink device is satisfied and the pl4 fifo channel credit counter decremen ts to 0), the pm3392 will buffer the incoming frames from the line side xsbi interface until a ll the buffer facilities within the pm3392 are exhausted. this buffer capacity includes both the allocated iflx ingress fifo buffer space and a 2kb (2048 bytes) receive buffer in the receive mac (rxxg). at this time the pm3392 will no longer accept data from the line side, resulting in overflow of the rxxg receive fifo. when buffer resources within the pm3392 become available, the rxxg will re-synchronize to the next start of a physical packet (preambl e/sfd delimiter) and continue ethernet frame reception. in the event that the pm3392 truncat es a frame because of lack of buffer space the frame will be marked as erred and is a countable event in the mstats receive counter frameslostduetointernalmacerror. whether th e received frame that was truncated in the rxxg receive fifo is forwarded to the iflx is determined by the setting of the fifo cut-thru threshold register, the point at which truncati on occurred, and whether any data from the frame had been transferred from the rxxg receive fifo to the iflx). any time an erred receive frame is forwarded to the iflx from the rxxg, the control word following the transfer of the last data byte of the erred frame on the pl4 bus will terminate with an end-of-packet status of abort. the iflx ingress fifo will absorb in-flight fra mes regardless of the paused flow-control state of the pm3392. the amount of ethernet frame data that can be received without exhausting receive buffer capabilities is related to: the buffer fill level at which the pause request was generated (for example, the ingress fifo high watermark register setting) the response of the link-partner to a pause request. the outgoing rate of frame data on the given channe l on the pl4 system-side. this is controlled by the system-side sink device using the fifo status signaling protocol and the pl4 output scheduling block (pl4mos) on the pm3392 device. 10.2.4 pl4 multi-channel output scheduler (pl4mos) the pl4 multi-channel output scheduler (pl4mo s) block is used to provide fairness when the iflx is configured for more than one channel of operation. since the pm3392 only has one channel the fairness operation of the pl4mos is not relevant. the pl4mos consists of three main blocks: the status calendar, the fairness controller, and the scheduling engine. the fair ness controller will not be discussed since this function is turned off in the s/uni-1x10ge due to only one channel being active. status calendar the status calendar communicates with the pl4 interface to obtain the fifo status (fs) on the pl4 system-side sink device. as described in the pl4 bus specification, the fifo status in the pl4mos is interpreted as a 2-bit code:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 68 document no.: pmc-2001304, issue 7 00 stv starving 01 hun hungry 10 sat satisfied 11 frm framing the status calendar is responsible for assigning credits based on the fifo status information received on the rstat[1:0] pins of the pm3392 device. the status calendar operates on the latest available fifo information. if a loss of synchronization is detected on the rs tat fifo status channel the status calendar resets the internal fifo status and clears the credit counters to zero. figure 11 state machine of a fifo channel blk cdt = 0 sat hun stv stv cdt <- m1 blk | cdt = 0 hun cdt <- max(cdt, m2) stv cdt <- m1 blk | cdt = 0 hun cdt <- max(cdt, m2) sat | 0 < cdt < m2 hun cdt <- max(cdt, m2) stv cdt <- m1 sat | 0 < cdt < m2 blk | cdt = 0 req cdt <- cdt - req req cdt <- cdt - req req cdt <- cdt - req
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 69 document no.: pmc-2001304, issue 7 figure 11 shows a state diagram for a single cha nnel and how the fifo status inputs affect the state machine of each channel. a 16-bit credit count er (cdt) is defined. this counter is set to maxburst1 when the fifo status is stv. if the rstat fifo status is updated to hun, the credit counter is set to the maximum of maxbur st2 and the current value of the credit counter. the values of maxburst1, maxburst2 are calculated based on the overall system latency and configuration and programmed into the pl4 mos maxburst1 and maxburst2 registers. scheduling engine the scheduling engine is responsib le for generating data transfer requests and sending them to the iflx. the scheduler generates the request b ased on two parameters. first is the status of the fifo whether it is hun, sat, stv or blk, where blk stands for blocked and will be explained later in this section. second is whet her the iflx has data ready for the fifo. the scheduler checks the status and if the iflx has data, if the status is hun or stv and the iflx has data ready, a service request is generated. every time the scheduler issues a request it updates the credit counter: it decrements the cu rrent value of cdt by a value, max_wrds, which is the minimum of the configur able pl4 maximum data burst length (max_transfer register) or the cdt counter. cdt = cdt ? min( max_transfer, cdt). 10.2.5 pl4 output interface the pl4 output interface implements the pl4 protocol as described in the pl4 bus specification (pmc-991635) via the rdclk+/-, rc tl+/-, and rdat[15:0]+/- device pins. in the block diagram, this datapath encompasses the pl4odp and part of the pl4io block. the pl4 interface provides a 16-bit wide data and in-band control stream, a single control signal and a dual-phase source synchronous clock in the forward path. the clock signal is either looptimed from the tdclk+/- or internally generated using the pl4_rclk+/- reference input. the control signal is used to identify the in-band cont rol words. in the retu rn path, the pl4 interface provides a two-bit fifo status bus with associat ed clock. all transmit and receive datapath signals and their associated data clock are differential lvds: rdclk+/-, rctl+/-, and rdat[15:0]+/- for ingress; tdclk+/-, tctl+/-, and tdat[15:0]+/- for egress. please refer to pmc-991635 for protocol details. the pl4 output interface takes a data stream provided by the iflx block, inserts in-band control (sof, eof status, dip4 code, channel a ddress) and bursts the stream across the pl4 bus to a system-side device in accordance to the pl4 protocol via the rctl+/- and rdat[15:0]+/- device pins. the data sink provides back to the pm3392 pl4 output interface fifo status indications using a 2-bit bus (rstat[1:0]) and as sociated clock (rsclk). these status signals are provided to the pl4mos block and are used in scheduling of data transfers from the iflx fifo to the pl4 bus.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 70 document no.: pmc-2001304, issue 7 the pl4 output interface allows for the tran smission of a training sequence to allow for dynamic de-skewing by a sink entity. the training sequence can be programmed to be a configurable number of consecutive pl4 bus training patterns. when possible, training patterns are stuffed into what would have been a sequen ce of twenty idle control characters: this does not affect normal frame data transfer. if a complete training sequence is sent within the configurable max_t number of pl4 bus cycles, th en normal frame data transfer will be held- off until a complete training sequence is sent. the minimum sop-to-sop spacing for data to be impressed on the pl4 bu s by the pm3392 is programmable to be a minimum of 2 or 8 pl4 bus cycles. all pl4 outputs from the pm3392 device are strictly compliant with the pos-phy level 4 specification. 10.3 transmit channel (egress) ? system side to line side 10.3.1 pl4 input interface the pl4 input interface implements the pl4 prot ocol as described in the pl4 bus specification (pmc-991635) via the tdclk+/-, tctl+/-, and tdat[15:0]+/- device pins. in the block diagram, this datapath encompasses the pl4i du and part of the pl4io block. the pl4 interface provides a 16-bit wide data and in-ba nd control stream, a single control signal and a dual-phase source synchronous clock in the forw ard path. all forward path signals are differential lvds. the tdclk+/- clock signal is required to be source-synchronous to the tctl+/- and tdat[15:0] signals. the control si gnal is used to identify the in-band control words. in the return path, the pl4 interface on the pm3392 drives a two-bit fifo status bus with associated clock (tstat[1:0] and tsclk). please refer to pmc-991635 for protocol details. the pl4 input interface sinks data and control on the pl4 bus: the data stream impressed on the tdat[15:0]+/- device pins is delineated us ing tctl+/-. the incoming stream of pl4 bus words is parsed according to the data path bus state diagram included in the pl4 specification. ethernet frame data is decapsulated in the in coming pl4 word stream and data bytes contained within a pl4 data burst are written into th e eflx egress fifo. pl4 control words are checked and extracted from th e incoming pl4 word stream. data must contain sufficient training pattern density to allow reliable operation of the data recovery and deskew units in the pl4io input l ogic. the pl4 bus specifies the transfer of un- encoded nrz data streams. consequently ther e may be arbitrarily long runs of consecutive zeros or ones. the pl4 input interface is capab le of properly recovering data once training has completed. a certain minimum rate of training pa tterns is required to ensure that data continues to be received without error. see the operations section for further details. the pos-phy level 4 specification defines correct operation, but generally does not define error handling except where it affects interoperab ility between the peer devices. consequently different devices may handle the same error differently.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 71 document no.: pmc-2001304, issue 7 the following simple rules are followed by th e pl4 input interface on the pm3392 device with respect to pl4 protocol errors: ? erroneous pl4 inputs (presented on pl4 tctl a nd tdat[15:0] pins) that could affect data integrity are strictly enforced. ? erroneous inputs that do not affect data integrity (length of training pattern, minimum sop spacing, etc) are only enforced to the extent that they actually cause problems for the state machines or data path. ? no single error will cause the data path (pl4 tc tl and tdat[15:0] pins) or the status path (pl4 rstat[1:0] pins) to lose synchronization. there is a link status state machine in the pl4 input interface to handle the tracking of errors with respect to the reception of non-erred training sequences. four link states are defined and can be read from the pl4idu status register: ? disable: awaiting the decode of a non-erred tr aining pattern. no data within a pl4 data burst will be forwarded to the downstream eflx from the pl4 input interface. ? run_green: have received at least one non-e rred training pattern and there have been no detected pl4 word parsing errors. data with in a pl4 data burst will be forwarded to the downstream eflx from the pl4 input interface. ? run_yellow: have detected one pl4 word parsing error since being in a run_green state. reception of a non-erred training pattern will result in a state change from run_yellow to run_green. reception of a pl4 word that has a detectable error will result in a state change from r un_yellow to run_orange. while in run_yellow, data within a pl4 data burst will be forwarded to the downstream eflx from the pl4 input interface. ? run_orange: have detected two pl4 wo rd parsing errors since being in a run_green state. data within a pl4 data burst will be forwarded to the downstream eflx from the pl4 input interface as long as a third pl4 word parsing error is not detected. reception of a non-erred training pattern will result in a state change from run_orange to run_green. reception of a pl4 word that has a detectable error will result in a state change from r un_orange to disable. while in run_orange, data within a pl4 data burst th at is non-erred will be forwarded to the downstream eflx from the pl4 input interface. in the event that the word parsing on the pl4 i nput interface detects an error (for example, the dip4 code check fails on the control word follo wing a pl4 data burst) in the pl4idu that have a pl4 port state of active or paused will be internally aborted. this will result in any ethernet frame data being written out to the eflx interface with the error flag set; the eflx fifo will subsequently propagate the frame data and error flag to the ethernet mac transmit interface. frame data terminated in this manne r will there be sent out the serial link interface as an erred ethernet transmit frame. the setting of th e error flag in the data sent from the eflx to the txxg is a detectable and countable event (mstat transmit statistics counter transmitsystemerror).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 72 document no.: pmc-2001304, issue 7 10.3.2 egress flexible fifo (eflx) the egress flexible fifo (eflx) provides a fifo to separate the system-side source timing of the pl4 bus interface from the ethernet mac (t xxg) transmit line-side timing. the eflx presents a single interface to the pl4 bus on the input side; on the output side the eflx connects to the transmit interface of the txxg block. the eflx provides 16kb (bytes of total buffering). the configuration of the buffer space cannot be done dynamically. changes to the buff er are to be done during device initialization. there is a minimum size required in order to guarantee that an almost-full condition on the egress fifo signaled via the tstat[1:0] pins of the pm3392 device will be able to absorb the maximum number of frame data bytes that can be in-flight. the fifo has a configurable low start threshold, a low watermark, and a high waterm ark. the low start threshold is used to allow accumulation of frame data before it is passed to the txxg interface. data is not forwarded from the egress fifo until the first of these conditions is met: ? the eop flag bit associated with the frame data in the egress fifo has been set ? the low start threshold on ethernet frame size for has been met by the frame data (programmable via the eflx indirect fifo cut-through register). this hold-off is done in order to avoid underr uns during transfer of the data to the txxg interface. the low and high watermarks are set to provide the pl4 bus fifo status signaling back to the system-side source device. refer to the operations section for additional details. 10.3.3 transmit 10g ethernet mac (txxg) the transmit 10g ethernet mac (txxg) pr ovides 10 gigabit media access control sub- layer processing on a single 10 gigabit ethernet stream. the txxg reads partially formed ethernet frames from the egress flexible fifo (eflx) and generates completely formed ethernet frames. the resulting frames are forward to the t64b66b block. the txxg implements the following principal functions: ? ethernet framing (optional insertion of an 8-by te preamble/start frame delimiter sequence, plus computation and optional insertion of a 32-bit fcs). ? frame timing relative to the system clock re ference input. the txxg will insert the correct programmable interframe gap between frame s to ensure that lan-mode operation conforms to the ieee 802.3 specification. in wan mode, no interframe gap is inserted; instead, the downstream payload processor is responsible for flow controlling the data stream. ? pause frame generation and insertion. the t xxg block will generate and format 64-byte pause mac control frames in response to requests from external blocks, with the specified pause timer values inserted at the proper location. generated pause frames are multiplexed into the outgoing frame stream in between data frames and with the proper spacing.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 73 document no.: pmc-2001304, issue 7 ? transmit pause implementation. pause frames received from the entity at the other end of the ethernet link must implement flow control by halting or resuming transmitted traffic. the txxg block provides the means for this to happen: pause timer values extracted from received pause frames can be input to the t xxg along with a notification signal, and will cause the txxg block to stop or restart traffic as required at the proper boundaries. ? transmit statistics support. after each data or pause frame has been transmitted, whether successfully or unsuccessfully, the txxg block out puts a statistics vector that signals the status of the transmission. this statistics vector is expected to be used by an external unit to update appropriate statistics counters. these counters in turn can be used to implement standard ethernet mibs for link management purposes. ? configuration and status maintenance. the in terframe gap, preamble, fcs generation, and error checking features of the txxg can be conf igured by means of internal configuration registers accessible via an ecbi bus interface. the following sections will describe the functi onality of each sub-block in more detail. mac incoming flow control state machine when a receive mac (rxxg) dec odes an error-free incoming 803.2 full-duplex flow control packet, the rxxg sends a pause signal to the txxg indicating that transmission is to be paused. the pause parameter is transferred to th e txxg unit, to apply to the local pause timer. this state-machine loads the timer (on request from the rxxg unit) and decrements the timer in units of pause interval . note, pause control frame transmission initiated using register bits is not affected by the pause pin. mac outgoing flow control state machine this state-machine monitors a high watermark fifo threshold level indication from the iflx or the external pause pin, and will issue a request to the mac core to transmit a mac control pause frames when required. when the mac core acknowledges this request, this state-machine will build the mac header and da ta frame, and present it to the mac core for transmission. the pause parameter value can be programmed using an internal register. pause control frames are injected (by the mac core) at the rate programmed using the pause timer interval register after the transmission of th e current frame. this periodic transmission will request the far end to xoff for the duration of the timer. when sending out control pause frames and a low watermark fifo indication from the iflx is detected, the mac core inserts a pause control frame with a pause timer value of 0 after the transmission of the current frame. this transm ission will request the far end to immediately xon. the transmit mac can also be directed by the ingress mac to halt data transmission to the line side. if the receive mac interprets a pause fra me, the transmit mac will be notified and also given a timer value. the transmit mac will halt transmission of data until the pause timer value has expired. while the transmit mac is halted, th e external paused pin to the line side will be asserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 74 document no.: pmc-2001304, issue 7 mac core the mac core is the heart of the txxg tsb a nd implements the principal functions of the ieee 802.3 mac layer. it consists of a state m achine, data steering and encapsulation logic, together with a 64-bit crc generator for co mputing the standard 32-bit ieee fcs. at any time, it may be operating in one of three modes: ? frame transmission disabled. ? mac flow control packet transmission enab led, when the mac incoming flow control state machine indicates the transmitter is paused. ? mac flow control and eflx-source packet tr ansmission enabled, with priority being given to mac flow control packet transmission, when not paused. during operation, the mac core waits until a frame is available to be sent, the downstream is requesting a packet for transmission and the inter- packet gap timer (ipg timer) is not active. it then generates the requisite preamble and sfd, and then transfers frame data from the packet source, 64 bits at a time. the sof/eof, error a nd valid signals supplied with the data words are processed to determine frame boundaries and contro l the crc generator, and also to determine intra-frame zero-padding and post-frame ipg spacing. the processed 64-bit data words are output to the downstream block. at the end of each frame transmission, the mac co re inserts an inter-frame gap of the required amount before starting the transfer of the next fra me. note that the interframe gap is counted in units of bytes rather than absolute time, perm itting frame timing to be done differently based on the application. after each packet transmit is completed, the mac core builds and transfers a transmit statistics vector to the mstat block. crc generator the crc checker performs a crc-32 calculation on the whole ethernet frame received using the standard ethernet polynomial. the crc generator performs a crc-32 calculati on on the whole ethernet frame using the standard ethernet polynomial. a parallel impl ementation of the crc polynomial is used. the result is optionally prepended to the frame. 10.3.4 transmit 64b66b encoder (t64b66b) the transmit 64b/66b processor implements a ll the required functiona lity of the 10 gigabit ethernet pcs sub-layer interface as specified in the unapproved ieee 802.3aestandard. it performs frame delineation on transmitted frame s from an upstream block, scrambles the frames, and 64b/66b encodes the scrambled stream . the resulting encoded stream is passed to a downstream device. in ieee mode, the t64b66b in put stream consists of standard ethernet (preamble/sfd, mac header, data, pad and crc) frames with possible intra-packet gaps (128-bit word gaps).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 75 document no.: pmc-2001304, issue 7 the t64b66b implements the following principal functions: ? ethernet frame delineation ? aligns to 32-bit sop boundaries ? 32 to 33 gearbox ? 64b/66b data encoding ? control code mapping ? data scrambling ? bit within byte ordering function ? transmit fault signaling ? transmit jitter test pattern generator tx pcs the tx pcs contains a finite state machine, which sequences through the 6 basic states shown in figure 12. it contains a scrambler based on g(x) = 1 + x 39 + x 58 . it provides all the timing and control necessary for capturing, aligning, an d processing the upstream data. the decision(s) for the transmit state machine to leave or re main in a given state are based upon the ieee 802.3ae standard. the tx pcs provides jitter test pattern generation as per ieee 802.3ae standard.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 76 document no.: pmc-2001304, issue 7 figure 12 tx processing steps for 66-bit codes power_on = true + reset init_done e processing state c processing state raw = s s processing state raw = d d processing state raw = t t processing state i processing state raw = e + d + t raw = e + d + t raw /= d raw = e + c + s raw = e + d + t raw = s raw = c raw = c + d + t from figure 12, the controller enters its initializa tion (i) state during reset or during a power-up sequence. to exit the i state, the input controlle r must wait for the internal data formatter and barrel shifter to sequence completely through their first 33 clock processing cycle, it also may wait for the de-assertion of an overhead mark er (depending on mode) from the downstream device and/or the assertion of a control detect indication from the data encoder block. given a successful execution of a proper initialization a nd the detection of the proper out-of-band control signals, the state machine will advance to its control code or (c) state. the c state processor will map only the incoming control cod es. upon detecting a valid sop transition, the state machine advances to the s processing state.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 77 document no.: pmc-2001304, issue 7 by looking at figure 12, a typical state sequence can be defined as: s, d, and t. the start of packet (s) state is entered via detection of the sop byte control indication. the data (d) state can consist of multiple (n) 66-bit frames. the end of packet (t) state is entered via detection of the eop byte control indication. in this case, according to the ieee 802.3ae specification, the outgoing eop byte can occur in anyone of eight possible locations within a 66-bit frame. an errored sequence would be any other type of tr ansition that doesn?t fo llow the simple sequence of start-of-packet state to the data capture st ate to the end-of-packet state. for example the following sequences: start-of-packet state to the e nd-of-packet state, start- of-packet state to the start-of-packet state, end-of-packet state to the data capture state, and data capture state to the start-of-packet state would be counted as e rrored sequences. after detection of an errored sequence the state machine always advances to the e state. during any errored state the proper errored frame will be sent downstream to the line interface. during a receiver error event: loss of signal (los), remote fault (rf), or local fault (lf) the input controller will immediately advance to the e state, where it will stay until the errored event is cleared. during los or lf the tx pcs will start sending remote fault messages continuously downstream. during rf the tx pcs will only send idles downstream. jitter test pattern generator when this is enabled via the jitt_pat_en (b it 6 of register 0x3080), the scrambler?s normal input data is ignored and two possible patterns are instead generated. if jtst_pat_sel (bit 7 of register 0x3080) is set to ?1? a square wave signal of the wavelength defined by swave_len+4 becomes the input to the scrambler. if instead jtst_pat_sel is set to ?0? then a pseudo random signal is ge nerated. this is done by: 1. setting the scrambler?s input to all zeros if the bit jdat_pat_sel(bit 8 of register 0x3080) equals ?1? or to the lf ordered set if jdat_pat_sel equals ?0?. 2. seeding the scrambler every 128 blocks where the seed value repeats as follows: a. seed a -> seed a inverse -> seed b -> seed b inverse -> seed a ? 10.4 management statistics (mstat) the mstat block is used to accumulate et hernet specific counts used for supporting management agents such rmon, snmp, and et herlike interfaces. the mstat supports full system probing capability via the use of full counter snapshot to shadow registers. incorporated into the mstat block is a fully programmable interrupt array enabling per counter rollover monitoring with interrupt reporting. ea ch mstat counter is 40-bits wide. 10.4.1 receive statistics counters with the receive statistics, there are 31 corresponding counters. they are defined in table 10.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 78 document no.: pmc-2001304, issue 7 table 10 receive statistics counters name of counter framesreceivedok octetsreceivedok framesreceived octetsreceived unicastframesreceivedok multicastframesreceivedok broadcastframesreceivedok taggedframesreceived pausemaccontrolframereceived maccontrolframereceived framechecksequenceerrors frameslostduetointernalmacerror symbolerror inrangelengtherrors framestoolongerrors jabbers fragments undersizedframes receiveframes64octets receiveframes65to127octets receiveframes128to255octets receiveframes256to511octets receiveframes512to1023octets receiveframes1024to1518octets (inc ludes tagged frames of 1522 bytes) receiveframes1519tomaxoctets jumbooctetsreceivedok filteredoctets filteredunicastframes filteredmulticastframes filteredbroadcastframes 10.4.2 transmit statistics counters with the transmit statistics, there are 22 corresponding counters. they are defined in table 11. table 11 transmit statistics counters name of counter framestransmittedok octetstransmittedok
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 79 document no.: pmc-2001304, issue 7 name of counter octetstransmitted frameslostduetointernalmactransmissionerror transmitsystemerror unicastframestransmittedattempted unicastframestransmittedok multicastframestransmittedattempted multicastframestransmittedok broadcastframestransmittedattempted broadcastframestransmittedok pausemacctrlframestransmitted macctrlframestransmitted transmittedframes64octets transmittedframes65to127octets transmittedframes128to255octets transmittedframes256to511octets transmittedframes512to1023octets transmittedframes1024to1518octets (i ncludes tagged frames of 1522 bytes) transmittedframes1519tomaxoctets jumbooctetstransmittedok 10.5 management data interface 10.5.1 description mdio (management data input/output) provi des communication between the host processor and an external physical device by means of a two-wire interface. the mdio block generates a clock (mdc) by dividing down the internal xsbi interface clock to provide timing reference for transfer of information on the mdi and mdo signal. mdio provides a mii management interface to transmit and receive management frame serially for the purpose of controlling the physical device and gathering status from the physical device. synchronization bits, selection addresses, and cont rol data and address to the external mii device are sent on the mdo. status data is received on mdi. mdoen is a tri-state driver enable for the mdo data. mdi and mdo are expect ed to be combined into a bi-directional pin external to this block. the port address bus prt adr[4:0] is used to select one of the 32 unique port and the device address bus devadr[4:0] is used to select a particular external physical device with which to communicate. 10.6 jtag test access port interface the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest instructions are supported. the s/uni-1x10ge identification code is 0x333920cd hexadecimal.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 80 document no.: pmc-2001304, issue 7 10.7 microprocessor interface the microprocessor interface block provides the logic required for interfacing the generic microprocessor bus with the normal mode and test mode registers within the s/uni-1x10ge. the normal mode registers are used during normal operation to configure and monitor the s/uni-1x10ge. the test mode registers are u sed to enhance the testability of the s/uni- 1x10ge. the register set is accessed as shown belo w. the address column of the table identifies the corresponding memory map address. addresses that are not shown are not used and must be treated as reserved. table 12 register memory map address hex base hex end register description 0x0000 0x0007 s/uni-1x10ge top level 0x0008 0x203f pm3392 reserved 0x2040 0x207f rxxg 0x2080 0x20bf r64b66b 0x20c0 0x20ff pm3392 reserved 0x2100 0x21ff mstat 0x2200 0x220f iflx 0x2210 0x223f pm3392 reserved 0x2240 0x224f pl4mos 0x2250 0x227f pm3392 reserved 0x2280 0x22bf pl4odp 0x22c0 0x22ff pm3392 reserved 0x2300 0x233f pl4io 0x2340 0x23ff pm3392 reserved 0x2400 0x241f iram 0x2420 0x303f pm3392 reserved 0x3040 0x307f txxg 0x3080 0x30bf t64b66b 0x30c0 0x31ff pm3392 reserved 0x3200 0x321f eflx 0x3220 0x327f pm3392 reserved 0x3280 0x32bf pl4idu 0x32c0 0x33ff pm3392 reserved 0x3400 0x341f eram 0x3420 0xffff pm3392 reserved
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 81 document no.: pmc-2001304, issue 7 11 normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-1x10ge. normal mode registers (as opposed to test mode registers) are selected when trs (a[14]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced vers ions of this product, unused register bits must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written in to can also be read back. this allows the processor controlling the s/uni-1x10ge to determine the programming state of the device. 3. write-able normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect s/uni-1x10ge operation unless otherwise noted. 5. certain register bits are reserved . these bits are associated with mega cell functions that are reserved in this application. to ensure that the s/uni-1x10ge operates as intended, reserved register bits must only be written with the logic level as specified. writing to reserved registers should be avoided. table 13 normal mode register map address a[14:0] register description top level registers 0x0000h identific ation register 0x0001h product revision register 0x0002h configuration a nd reset control register 0x0003h master interrupt status register 0x0004h device status register 0x0005h global performance monitor update 0x0006h mdio command register 0x0007h mdio interrupt mask register 0x0008h mdio interrupt register 0x0009h mmd phy address register 0x000ah mmd control data address register 0x000bh mmd read status data register 0x000ch 0x00ff pm3392 reserved 0x0100h xsbi configuration register
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 82 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x0101h reserved 0x0102h reserved 0x0103h xbsi rxfifoslipi 0x0104h xsbi interrupt 0x0105h reserved 0x0106h reserved 0x0107h xsbi interrupt mask2 0x0108h xsbi interrupt mask3 0x0109h xsbi rxoolv 0x010ah xsbi analog debug 0x0200h 0x020f mdio 0x010bh 0x203f pm3392 reserved rxxg specific registers 0x2040h configuration 1 0x2041h configuration 2 0x2042h configuration 3 0x2043h interrupt 0x2044h status 0x2045h maximum frame size 0x2046h station address, low 16 bits 0x2047h station address, middle 16 bits 0x2048h station address, high 16 bits 0x2049h receive fifo threshold 0x204ah exact match address 0 low word 0x204bh exact match address 0 mid word 0x204ch exact match address 0 high word 0x204dh exact match address 1 low word 0x204eh exact match address 1 mid word 0x204fh exact match address 1 high word 0x2050h exact match address 2 low word 0x2051h exact match address 2 mid word 0x2052h exact match address 2 high word 0x2053h exact match address 3 low word 0x2054h exact match address 3 mid word 0x2055h exact match address 3 high word 0x2056h exact match address 4 low word 0x2057h exact match address 4 mid word 0x2058h exact match address 4 high word 0x2059h exact match address 5 low word 0x205ah exact match address 5 mid word
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 83 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x205bh exact match address 5 high word 0x205ch exact match address 6 low word 0x205dh exact match address 6 mid word 0x205eh exact match address 6 high word 0x205fh exact match address 7 low word 0x2060h exact match address 7 mid word 0x2061h exact match address 7 high word 0x2062h exact match vid 0 0x2063h exact match vid 1 0x2064h exact match vid 2 0x2065h exact match vid 3 0x2066h exact match vid 4 0x2067h exact match vid 5 0x2068h exact match vid 6 0x2069h exact match vid 7 0x206ah multicast hash low word 0x206bh multicast hash midlow word 0x206ch multicast hash midhigh word 0x206dh multicast hash high word 0x206eh address filter control 0 0x206fh address filter control 1 0x2070h address filter control 2 0x2071h filter error counter 0x2072h 0x207f rxxg reserved r64b66b specific registers 0x2080h r64b66b configuration 0x2081h r64b66b interrupt mask 0x2082h r64b66b interrupt status 0x2083h r64b66b status 0x2084h r64b66b error frame count 0x2085h r64b66b error lock counter 0x2086h r64b66b high bit error rate 0x2087h 0x20bf r64b66b reserved 0x20c0h 0x20ff pm3392 reserved mstat specific registers 0x2100h mstat control 0x2101h mstat counter rollover 0 0x2102h mstat counter rollover 1 0x2103h mstat counter rollover 2 0x2104h mstat counter rollover 3
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 84 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x2105h mstat interrupt mask 0 0x2106h mstat interrupt mask 1 0x2107h mstat interrupt mask 2 0x2108h mstat interrupt mask 3 0x2109h mstat counter write address 0x210ah mstat counter write data low 0x210bh mstat counter write data middle 0x210ch mstat counter write data high 0x210dh 0x210f mstat reserved 0x2110h low framesreceivedok 0x2111h med 0x2112h high 0x2113h mstat reserved 0x2114h low octetsreceivedok 0x2115h med 0x2116h high 0x2117h mstat reserved 0x2118h low framesreceived 0x2119h med 0x211ah high 0x211bh mstat reserved 0x211ch low octetsreceived 0x211dh med 0x211eh high 0x211fh mstat reserved 0x2120h low unicastframesreceivedok 0x2121h med 0x2122h high 0x2123h mstat reserved 0x2124h low multicastframesreceivedok 0x2125h med 0x2126h high 0x2127h mstat reserved 0x2128h low broadcastframesreceivedok 0x2129h med 0x212ah high 0x212bh mstat reserved 0x212ch low taggedframesreceived 0x212dh med 0x212eh high
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 85 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x212fh mstat reserved 0x2130h low pausemaccontrolframereceived 0x2131h med 0x2132h high 0x2133h mstat reserved 0x2134h low maccontrolframereceived 0x2135h med 0x2136h high 0x2137h mstat reserved 0x2138h low framechecksequenceerrors 0x2139h med 0x213ah high 0x213bh mstat reserved 0x213ch low frameslostduetointernalmacerror 0x213dh med 0x213eh high 0x213fh mstat reserved 0x2140h low symbolerror 0x2141h med 0x2142h high 0x2143h mstat reserved 0x2144h low inrangelengtherrors 0x2145h med 0x2146h high 0x2147h mstat reserved 0x2148h low reserved 0x2149h med 0x214ah high 0x214bh mstat reserved 0x214ch low framestoolongerrors 0x214dh med 0x214eh high 0x214fh mstat reserved 0x2150h low jabbers 0x2151h med 0x2152h high 0x2153h mstat reserved 0x2154h low fragments 0x2155h med 0x2156h high
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 86 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x2157h mstat reserved 0x2158h low undersizedframes 0x2159h med 0x215ah high 0x215bh mstat reserved 0x215ch low receiveframes64octets 0x215dh med 0x215eh high 0x215fh mstat reserved 0x2160h low receiveframes65to127octets 0x2161h med 0x2162h high 0x2163h mstat reserved 0x2164h low receiveframes128to255octets 0x2165h med 0x2166h high 0x2167h mstat reserved 0x2168h low receiveframes256to511octets 0x2169h med 0x216ah high 0x216bh mstat reserved 0x216ch low receiveframes512to1023octets 0x216dh med 0x216eh high 0x216fh mstat reserved 0x2170h low receiveframes1024to1518octets 0x2171h med 0x2172h high 0x2173h mstat reserved 0x2174h low receiveframes1519tomaxoctets 0x2175h med 0x2176h high 0x2177h mstat reserved 0x2178h low jumbooctetsreceivedok 0x2179h med 0x217ah high 0x217bh mstat reserved 0x217ch low filteredoctets 0x217dh med 0x217eh high
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 87 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x217fh mstat reserved 0x2180h low filteredunicastframes 0x2181h med 0x2182h high 0x2183h mstat reserved 0x2184h low filteredmulticastframes 0x2185h med 0x2186h high 0x2187h mstat reserved 0x2188h low filteredbroadcastframes 0x2189h med 0x218ah high 0x218bh mstat reserved 0x218ch low reserved 0x218dh med 0x218eh high 0x218fh mstat reserved 0x2190h low framestransmittedok 0x2191h med 0x2192h high 0x2193h mstat reserved 0x2194h low octetstransmittedok 0x2195h med 0x2196h high 0x2197h mstat reserved 0x2198h low octetstransmitted 0x2199h med 0x219ah high 0x219bh mstat reserved 0x219ch low frameslostduetointernalmactransmissionerror 0x219dh med 0x219eh high 0x219fh mstat reserved 0x21a0h low transmitsystemerror 0x21a1h med 0x21a2h high 0x21a3h mstat reserved 0x21a4h low unicastframestransmittedattempted 0x21a5h med 0x21a6h high
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 88 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x21a7h mstat reserved 0x21a8h low unicastframestransmittedok 0x21a9h med 0x21aah high 0x21abh mstat reserved 0x21ach low multicastframestransmittedattempted 0x21adh med 0x21aeh high 0x21afh mstat reserved 0x21b0h low multicastframestransmittedok 0x21b1h med 0x21b2h high 0x21b3h mstat reserved 0x21b4h low broadcastframestransmittedattempted 0x21b5h med 0x21b6h high 0x21b7h mstat reserved 0x21b8h low broadcastframestransmittedok 0x21b9h med 0x21bah high 0x21bah mstat reserved 0x21bch low pausemacctrlframestransmitted 0x21bdh med 0x21beh high 0x21bfh mstat reserved 0x21c0h low macctrlframestransmitted 0x21c1h med 0x21c2h high 0x21c3h mstat reserved 0x21c4h low transmittedframes64octets 0x21c5h med 0x21c6h high 0x21c7h mstat reserved 0x21c8h low transmittedframes65to127octets 0x21c9h med 0x21cah high 0x21cbh mstat reserved 0x21cch low transmittedframes128to255octets 0x21cdh med 0x21ceh high
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 89 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x21cfh mstat reserved 0x21d0h low transmittedframes256to511octets 0x21d1h med 0x21d2h high 0x21d3h mstat reserved 0x21d4h low transmittedframes512to1023octets 0x21d5h med 0x21d6h high 0x21d7h mstat reserved 0x21d8h low transmittedf rames1024to1518octets 0x21d9h med 0x21dah high 0x21dbh mstat reserved 0x21dch low transmittedframes1519tomaxoctets 0x21ddh med 0x21deh high 0x21dfh mstat reserved 0x21e0h low jumboo ctetstransmittedok 0x21e1h med 0x21e2h high 0x21e3h mstat reserved 0x21e4h low reserved 0x21e5h med 0x21e6h high 0x21e7h mstat reserved 0x21e8h reserved 0x21e9h reserved 0x21eah 0x21ff mstat reserved iflx specific registers 0x2200h iflx global configuration register 0x2201h iflx channel provision 0x2202h iflx global status register 0x2203h iflx sof error enable 0x2204h iflx sof error interrupt 0x2205h iflx eof error enable 0x2206h iflx eof error interrupt 0x2207h reserved 0x2208h reserved 0x2209h iflx fifo overflow enable 0x220ah iflx fifo overflow interrupt
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 90 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x220bh iflx tag processor error enable 0x220ch reserved 0x220dh reserved 0x220eh iflx indirect logical fifo low limit & provision 0x220fh iflx indirect logical fifo high limit 0x2210h iflx indirect full/almost full status & limit 0x2211h iflx indirect empty/almost empty status & limit 0x2212h reserved 0x2213h reserved 0x2214h reserved 0x2215h reserved 0x2216h reserved 0x2217h reserved 0x2218h 0x223f iflx reserved pl4mos specific registers 0x2240h pl4mos configuration register 0x2241h pl4mos mask register 0x2242h pl4mos fairness masking register 0x2243h pl4mos maxburst1 register 0x2244h pl4mos maxburst2 register 0x2245h pl4mos transfer size register 0x2247h reserved 0x2248h reserved 0x2249h reserved 0x224ah reserved 0x224bh reserved 0x224ch reserved 0x224dh reserved 0x224eh reserved 0x224fh reserved 0x2250h 0x225f reserved 0x2260h 0x226f reserved 0x2270h 0x227f pl4mos reserved pl4odp specific registers 0x2280h pl4odp configuration 0x2281h pl4odp status 0x2282h pl4odp interrupt mask 0x2283h pl4odp interrupt 0x2284h pl4odp confi guration max_t register 02285h pl4odp elastic store limit
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 91 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x2286h reserved 0x2287h reserved 0x2288h reserved 0x2289h reserved 0x228ah reserved 0x228bh reserved 0x228ch reserved 0x228dh reserved 0x228eh reserved 0x228fh reserved 0x2290h reserved 0x2291h reserved 0x2292h reserved 0x2293h reserved 0x2294h reserved 0x2295h reserved 0x2296h reserved 0x2297h reserved 0x2298h reserved 0x2299h reserved 0x229ah reserved 0x229bh reserved 0x229ch reserved 0x229dh reserved 0x229eh 0x22ff f pl4odp reserved pl4io specific registers 0x2300h pl4io lock detect status 0x2301h pl4io lock detect change 0x2302h pl4io lock detect mask 0x2303h pl4io lock detect limits 0x2304h pl4io calendar repetitions 0x2305h pl4io configuration 0x2306h reserved 0x2307h reserved 0x2308h reserved 0x2309h reserved 0x230ah reserved 0x230bh reserved 0x230ch reserved
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 92 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x230dh reserved 0x230e reserved 0x230fh reserved 0x2310h reserved 0x2311h reserved 0x2312h 0x2313h 0x2314h 0x2315h 0x2316h 0x231f 0x2320h 0x2321h 0x2322h 0x2323h 0x2324h 0x2325h 0x2326h 0x2327h 0x2328h 0x2329h 0x232ah 0x232bh 0x232ch 0x232dh 0x232eh 0x232fh 0x2330h 0x2331h 0x233f pl4io reserved 0x2340h 0x23ff pm3392 reserved txxg specific registers 0x3040h configuration register 1 0x3041h configuration register 2 0x3042h configuration register 3 0x3043h interrupt register 0x3044h status register 0x3045h transmit max frame size register 0x3046h transmit min frame size register 0x3047h station address, low 16 bits 0x3048h station address, middle 16 bits 0x3049h station address, high 16 bits
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 93 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x304ah diagnostic register 1 0x304bh diagnostic register 2 0x304ch diagnostic status register 0x304dh pause timer register 0x304eh pause timer interval register 0x304fh packet statistics register low 14 bits 0x3050h packet statistics register high 16 bits 0x3051h filter error count register 0x3052 pause quantum value configuration 0x3053h 0x307f txxg reserved t64b66b specific registers 0x3080h t64b66b configuration 0x3081h t64b66b interrupt mask 0x3082h t64b66b interrupt status 0x3083h t64b66b status 0x3084h t64b66b store threshold 0x3085h 0x31ff pm3392 reserved eflx specific registers 0x3200h global configuration 0x3201h ercu global status 0x3202h indirect channel address 0x3203h indirect fifo low limit 0x3204h indirect fifo high limit 0x3205h indirect full/almost-full status and limit 0x3206h indirect empty/almost-empty status and limit 0x3207h indirect fifo cut-through threshold 0x3208h fifo sof error enable 0x3209h fifo sof error indication 0x320ah fifo eof error enable 0x320bh fifo eof error indication 0x320ch fifo overflow error enable 0x320dh fifo overflow error indication 0x320eh invalid channel error enable 0x320fh invalid channel error indication 0x3210h channel provision 0x3211h 0x3216 unused, reserved 0x3217h reserved 0x3218h reserved 0x3219h reserved 0x321ah reserved
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 94 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x321bh reserved 0x321ch reserved 0x321dh 0x327f pm3392 reserved pl4idu specific registers 0x3280h pl4idu configuration 0x3281h pl4idu status 0x3282h pl4idu interrupt mask 0x3283h pl4idu interrupt 0x3284h reserved 0x3285h reserved 0x3286h reserved 0x3287h reserved 0x3288h reserved 0x3289h reserved 0x328ah reserved 0x328bh reserved 0x328ch reserved 0x328dh reserved 0x328eh reserved 0x328fh reserved 0x3290h reserved 0x3291h reserved 0x3292h reserved 0x3293h reserved 0x3294h reserved 0x3295h reserved 0x3296h reserved 0x3297h reserved 0x3298h reserved 0x3299h reserved 0x329ah reserved 0x329bh reserved 0x329ch reserved 0x329dh reserved 0x329eh reserved 0x329fh reserved 0x32a0h reserved 0x32a1h reserved 0x32a2h reserved 0x32a3h reserved
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 95 document no.: pmc-2001304, issue 7 address a[14:0] register description 0x32a4h reserved 0x32a5h reserved 0x32a6h reserved 0x32a7h reserved 0x32a8h reserved 0x32a9h reserved 0x32aah reserved 0x32abh reserved 0x32ach reserved 0x32adh reserved 0x32aeh reserved 0x32afh reserved 0x32b0h reserved 0x32b1h reserved 0x32b2h reserved 0x32b3h reserved 0x32b3h 0x32bf pl4idu reserved 0x32c0h 0x33ff pm3392 reserved
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 96 document no.: pmc-2001304, issue 7 register 0x0000h:pm3392 identification bit type function default bit 15 r id[15] 0 bit 14 r id[14] 0 bit 13 r id[13] 1 bit 12 r id[12] 1 bit 11 r id[11] 0 bit 10 r id[10] 0 bit 9 r id[9] 1 bit 8 r id[8] 1 bit 7 r id[7] 1 bit 6 r id[6] 0 bit 5 r id[5] 0 bit 4 r id[4] 1 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 1 bit 0 r id[0] 0 id[15:0] the identification register presents a valid pm c product id number for the device. this register is read only. the default value is 0x3392.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 97 document no.: pmc-2001304, issue 7 register 0x0001h:pm3392 product revision bit type function default bit 15 r revision[15] 0 bit 14 r revision[14] 0 bit 13 r revision[13] 0 bit 12 r revision[12] 0 bit 11 r revision[11] 0 bit 10 r revision[10] 0 bit 9 r revision[9] 0 bit 8 r revision[8] 0 bit 7 r revision[7] 0 bit 6 r revision[6] 0 bit 5 r revision[5] 0 bit 4 r revision[4] 0 bit 3 r revision[3] 0 bit 2 r revision[2] 0 bit 1 r revision[1] 1 bit 0 r revision[0] 1 revision[15:0] this register is read only. this register presents the current device revision number. the default value is 0x0003.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 98 document no.: pmc-2001304, issue 7 register 0x0002h:pm3392 configuration and reset control bit type function default bit 15 r top_chan[3] 0 bit 14 r top_chan[2] 0 bit 13 r top_chan[1] 0 bit 12 r top_chan[0] 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r/w reserved 0 bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r/w xsbi aresetb 1 bit 1 r/w aresetb 1 bit 0 r/w dresetb 1 the reset control register provides configuration related to reset operation on the pm3392. dresetb the dresetb bit (low-true) allows the digita l circuitry in the pm3392 to be reset under software control. setting this bit to logic 0 will cause the digital portion of the device to be held in reset. this bit is not self-clearing. please refer to the operations section of this document for instructions concerning resetti ng the pm3392 device. performing a hardware reset will set this bit to logic 1, thus negating the digital software reset. aresetb the aresetb bit (low-true) allows all anal og circuitry related to the pl4 bus analog circuitry to be reset under software control. writing this bit to a logic 0 will cause the pl4 analog circuitry to be held in reset. this bit is not self-clearing and must be written to logic 1 to de-assert. please refer to the operati ons section of this document for instructions concerning resetting the pm3392 device. performi ng a hardware reset (that is, forcing the device rstb pin to a logic 0) will set the ar esetb bit to logic 1, thus negating the analog software reset.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 99 document no.: pmc-2001304, issue 7 xsbi aresetb the xsbi aresetb bit (low-true) allows all analog circuitry related to the xsbi bus analog circuitry to be reset under software control. writing this bit to a logic 0 will cause the xsbi analog circuitry to be held in reset. once set to 0, internal clocks generated from the line side to the core will not be reliable. this bit is not self-clearing and must be written to logic 1 to de-assert. top_chan[3:0] top_chan[3:0] is the id number of the highest active channel on the pm3392 device. this field is read only and set to 0.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 100 document no.: pmc-2001304, issue 7 register 0x0003h:pm3392 master interrupt status bit type function default bit 15 r/w inte 0 bit 14 r iram_int bit 13 r eram_int bit 12 r xsbi_int bit 11 r mstat_int bit 10 r rxxg_int bit 9 r txxg_int bit 8 r r64b66b_int bit 7 r t64b66b_int bit 6 r mdio_busy_int bit 5 r pl4_dool_int bit 4 r pl4_rool_int bit 3 r iflx_int bit 2 r eflx_int bit 1 r pl4odp_int bit 0 r pl4idu_int this master interrupt status register allows th e source of an active interrupt to be identified down to the block level. further register acce sses are required to the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. reading of this register has no side effects. interrupt stat us is set to logic 1 to indicate a pending interrupt of the specified type. pl4idu_int interrupt status indicator for the pl4idu block. pl4odp_int interrupt status indicator for the pl4odp block. eflx_int interrupt status indicator for the eflx block. iflx_int interrupt status indicator for the iflx block.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 101 document no.: pmc-2001304, issue 7 pl4_rool_int pl4 reference out of lock interrupt status. th is is the interrupt status indicator for the pl4io block indicating that the reference out of lock condition has changed state. pl4io_dool_int pl4io data out of lock interrupt status. th is is the interrupt status indicator for the pl4io block indicating that the data out of lock condition has changed state. mdio_busy_int mdio busy int is asserted with the rising edge of lctld, lctla, rstat, or rdinc in the mdio command register. this indicat es that the management interface has an operation in progress. t64b66b_int interrupt status indicator for the t64b66b block. r64b66b_int interrupt status indicator for the r64b66b block. mstat_int interrupt status indicator for one of the ten mstat blocks. identification of which mstat channels have active interrupts can be done using the pm3392 mstat interrupt status register. xsbi_int interrupt status indicator for the xsbi block. eram_int interrupt status indicator for the eflx ram block. iram_int interrupt status indicator for the iflx ram block.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 102 document no.: pmc-2001304, issue 7 inte the interrupt enable (inte) bit controls th e assertion of the interrupt (intb) output. when logic 1 is written to inte, the pending interr upt(s) listed in this register will assert the interrupt (intb) output. when logic 0 is writte n to inte, the pending interrupt(s) will not assert the interrupt (intb) output.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 103 document no.: pmc-2001304, issue 7 register 0x0004h:pm3392 device status bit type function default bit 15 r unused bit 14 r unused bit 13 r unused bit 12 r unused bit 11 r unused bit 10 r unused bit 9 r unused bit 8 r mdio_busy bit 7 r dtrb bit 6 r expired bit 5 r paused bit 4 r pl4_id_dool bit 3 r pl4_is_dool bit 2 r pl4_id_rool bit 1 r pl4_is_rool bit 0 r pl4_out_rool the pm3392 device status register provides the ability to monitor device operation. pl4_out_rool pl4 output reference out of lock status. pl4_out_rool is a logic 1 if the synthesized clock associated with the pl4 output interface is not trained to the reference frequency. pl4_out_rool is a logic 0 otherwise. the pl4 data and status output interfaces (pm3392 device pins rdclk+/-, rdat[15:0]+/-, rctl+/-, tstat[1:0], and tsclk) are normally disabled when pl4_out_rool is asser ted. all of the pl4io interfaces share a single clock synthesizer. pl4_is_rool pl4 input status reference out of lock conditio n. pl4_is_rool is a logic 1 if the input fifo status clock (pm3392 device pin rs clk) frequency exceeds ? the frequency of device pin rdclk+/-. pl4_is_rool is a logic 0 otherwise. the pl4 input status interface (pm3392 device pins rstat[1:0]) is normally disabled when pl4_is_rool is a logic 1.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 104 document no.: pmc-2001304, issue 7 pl4_id_rool pl4 input data reference out of lock cond ition. pl4_id_rool is a logic 1 if the parallel data input clock (pm 3392 device pin tdclk+/-) or one or more of the parallel data input streams (pm3392 device pins tdat[ 15:0]+/- and tctl+/-) is not trained to the local synthesized clock. pl4_id_rool is a logic 0 otherwise. the pl4 data input interface is normally disabled when pl4_id_rool is asserted. pl4_is_dool pl4 input status out of lock condition. pl4_is_dool is a logic 1 if the parallel fifo status input stream is not properly synchronized. pl4_is_dool is a logic 0 otherwise. pl4_id_dool pl4 input data out of lock condition. pl4_id_dool is a logic 1 if the parallel input data stream is not prope rly aligned. pl4_id_dool is a logic 0 otherwise. paused the paused signal indicates the reception and execution of mac control pause frames on the pm3392. if paused is logic 1, then the pm3392 is in the paused state and mac data frame transmission is blocked. if paused is a logic 0, then it is not in a paused state. expired expired is used by the device to deassert di gital reset (drstb) after the analog clocks have had time to stabilize. this indicates that the pl4 analog block has come out of reset. expired is deasserted when prstb is asserted. expired is asserted 10.0 to 13.5 ms (nominal) after prstb is deasserted, and remains asserted thereafter. dtrb digital timer reset, dtrb, is used to overri de the internal timer supplied by the pl4 analog. the internal timer determines the amount of time before clocks are reliable from the clock recovery logic. dtrb is an external pin used during power-up reset to override this timer. this pin is normally held low, but driven high to override. mdio_busy mdio busy is used to indicate that the md io block has an operation in progress. the register can be used for polling.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 105 document no.: pmc-2001304, issue 7 register 0x0005h:pm3392 global performance monitor update bit type function default bit 15 r/w tip x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r unused x bit 0 r unused x writing to this register performs a global performance monitor update by simultaneously loading all the performance meter registers in the pl4idu and pl4odp blocks. tip the tip bit is set to a logic one when the performance meter registers are being loaded. writing to this register with dreset equal to logic 0 initiates an accumulation interval transfer and loads all the performance meter registers in the pm3392. tip remains logic 1 while the transfer is in progress, and is set to a logic zero when the transfer is complete. tip can be polled by a microprocessor to determine when the accumulation interval transfer is complete.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 106 document no.: pmc-2001304, issue 7 register 0x0006h:mdio command register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r/w rdinc 0 bit3 r/w rstat 0 bit 2 r/w lctld 0 bit 1 r/w lctla 0 bit 0 r/w spre 0 spre this bit controls the preamble suppression in the mdio block. when ?0? the mdio sends a sequence of 32 contiguous logic one bit on the mdo pin that can be used to establish synchronization. when ?1? the mdio suppresses the 32-bit preamble. this bit must be written to the inac tive state to complete the operation or begin a new operation. lctla a 0 to 1 transition on this bit causes the mdio block to send a management frame with payload containing address of the register to be accessed in the subsequent operation. this bit must be written to the inactive state to co mplete the operation or begin a new operation. lctld a 0 to 1 transition on this bit causes the mdio block to send a management frame with payload containing control data to be written to the register whose address was provided in the previous address frame. this bit must be written to the inactive state to complete the operation or begin a new operation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 107 document no.: pmc-2001304, issue 7 rstat a 0 to 1 transition on this bit causes the mdio block to send a read operation management frame. the mdio reads status from the external mii phy register whose address is specified in the previous address frame. this bit must be written to the inactive state to complete the operation or begin a new operation. rdinc a 0 to 1 transition on this bit causes the md io block to send a post-read-increment-address operation management frame. this bit must be written to the inactive state to complete the operation or begin a new operation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 108 document no.: pmc-2001304, issue 7 register 0x0007h:mdio interrupt mask register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r unused x bit 0 r/w busye 0 busye when ?1?, busyi in the mdio interrupt register will assert the int pin when interrupts are enabled. when ?0?, the busyi interrupt will have no effect on the interrupt pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 109 document no.: pmc-2001304, issue 7 register 0x0008h:mdio interrupt register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r unused x bit 0 r busyi 0 busyi when ?1? indicates mdio operation is in progress, busy is asserted with the rising edge of lctld, lctla, rstat, or rdinc in the mdio command register. when ?0? indicates the end of operation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 110 document no.: pmc-2001304, issue 7 register 0x0009h:mmd phy address register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r/w devadr[4] 0 bit 11 r/w devadr[3] 0 bit 10 r/w devadr[2] 0 bit 9 r/w devadr[1] 0 bit 8 r/w devadr[0] 0 bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r/w prtadr[4] 0 bit3 r/w prtadr[3] 0 bit 2 r/w prtadr[2] 0 bit 1 r/w prtadr[1] 0 bit 0 r/w prtadr[0] 0 prtad[4:0] this is a 5-bit port address allowing 32 unique port addresses per mdio. the first port address bit to be transmitted is the msb of the address. devadr[4:0] this is a 5-bit device address, allows 32 unique devices per port. the first device address bit to be transmitted is the msb of the address.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 111 document no.: pmc-2001304, issue 7 register 0x000ah:mmd control address data register bit type function default bit 15 r/w ctlad[15] 0 bit 14 r/w ctlad[14] 0 bit 13 r/w ctlad[13] 0 bit 12 r/w ctlad[12] 0 bit 11 r/w ctlad[11] 0 bit 10 r/w ctlad[10] 0 bit 9 r/w ctlad[9] 0 bit 8 r/w ctlad[8] 0 bit 7 r/w ctlad[7] 0 bit 6 r/w ctlad[6] 0 bit 5 r/w ctlad[5] 0 bit 4 r/w ctlad[4] 0 bit 3 r/w ctlad[3] 0 bit 2 r/w ctlad[2] 0 bit 1 r/w ctlad[1] 0 bit 0 r/w ctlad[0] 0 ctlad[15:0] control address/data input bus. this register is used for indexing a 16-bit address into the external device during a control sequence. wh en expecting a data during a write command, this register will contain the resultant data.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 112 document no.: pmc-2001304, issue 7 register 0x000bh:mdio read status data register bit type function default bit 15 r prsd[15] 0 bit 14 r prsd[14] 0 bit 13 r prsd[13] 0 bit 12 r prsd[12] 0 bit 11 r prsd[11] 0 bit 10 r prsd[10] 0 bit 9 r prsd[9] 0 bit 8 r prsd[8] 0 bit 7 r prsd[7] 0 bit 6 r prsd[6] 0 bit 5 r prsd[5] 0 bit 4 r prsd[4] 0 bit 3 r prsd[3] 0 bit 2 r prsd[2] 0 bit 1 r prsd[1] 0 bit 0 r prsd[0] 0 prsd[15:0] read status data. the 16-bit result from the mdio read operation whose address is specified in the previous address frame.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 113 document no.: pmc-2001304, issue 7 register 0x0100h:xsbi wrapper configuration register bit type function default bit 15 r reserved bit 14 r reserved bit 13 r unused bit 12 r unused bit 11 r unused bit 10 r reserved bit 9 r/w sync_err_inv 0 bit 8 r/w xsbi_en 0 bit 7 r/w atmen 0 bit 6 r reserved 0 bit 5 r/w local_loopback_en 0 bit 4 r/w oifs_en 1 bit3 r/w mpgm_mon_en 0 bit 2 r/w mpgm_gen_en 0 bit 1 r/w bit_swizzle 0 bit 0 r/w phase_init 0 phase_init this bit controls the logic level of the phase_init output pin. when '0' sets the phase_init output pin low. when '1' sets the phase_init output pin high bit_swizzle when '0' the chip is in the default l an mode and the bit order is not altered when '1', it reverses the bit order in the 16-b it rxdatai_j (i=1 to 4, j=1 to 4) on the rx side and txdatai_j (i=1 to 4, j=1 to 4) on the tx side. rx side: rxdata4_4 becomes rxdata1_1 rxdata4_3 becomes rxdata1_2 rxdata1_1 becomes rxdata4_4 mpgm_gen_en when ?0?, the xsbi_wrapper is in normal functional mode and the mpgm generator on the transmit side is disabled.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 114 document no.: pmc-2001304, issue 7 when ?1?, the xsbi_wrapper is in diagnos tic mode and the mpgm generator on the transmit side is enabled. this bit enables the transmit prbs testing. mpgm_mon_en when ?0?, the xsbi_wrapper is in normal f unctional mode and the mpgm monitor on the receive side is disabled. when ?1?, the xsbi_wrapper is in diagnos tic mode and the mpgm generator on the receive side is enabled. this bit enables the receive prbs testing. oifs_en (input to the oifs abc) when ?1?, oifs abc is in normal operation. when ?0?, power to the oifs abc is shut down. local_loopback_en when '0' the xsbi_wrapper is in normal functional mode. when '1' the xsbi_wrapper is in diagnostic mode. the local system side loopback mode is enabled. the transmit data from the transmit pcs is looped back to the receive pcs. to write to this bit the xsbi_en bit (bit 8) must be set to 0 first, then write the local_loopback_en bit. atmen (input to the oifs abc) when ?0? oifs abc is in normal operational mode. when ?1? oifs abc is in analog test mode. xsbi_en when '0 the data will not be forwarded to and from the pcs block. when '1' the xsbi_wrapper block will be in normal operational mode. sync_err_inv sync_err_inv is used to supply an inversi on feature when the external driving pin is signal_detect instead of sync_err. this will make the pm3392 more compatible with other optics. when '0', the sync error input signal will be unaltered.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 115 document no.: pmc-2001304, issue 7 when '1', the sync error input will be inverted. bit type function default bit 15 r rxooli15 0 bit 14 r rxooli14 0 bit 13 r rxooli13 0 bit 12 r rxooli12 0 bit 11 r rxooli11 0 bit 10 r rxool10 0 bit 9 r rxooli9 0 bit 8 r rxooli8 0 bit 7 r rxooli7 0 bit 6 r rxooli6 0 bit 5 r rxooli5 0 bit 4 r rxooli4 0 bit 3 r rxooli3 0 bit 2 r rxooli2 0 bit 1 r rxooli1 0 bit 0 r rxooli0 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 116 document no.: pmc-2001304, issue 7 register 0x0104h:xsbi interrupt status bit type function default bit 15 r reserved 0:high bit 14 r reserved 0:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r unused x:high bit 4 r unused x:high bit 3 r unused x:high bit 2 r txfifoslipi 0 bit 1 r sync_erri 0 bit 0 r phase_erri 0 phase_erri when ?1? indicates that the input pin phase_err is asserted and output clock pin txclk2+/- is not aligned with the corresponding output data bus txdata+/-. sync_erri when '1' indicates that the input pin sync_err is asserted and input data, rxdata+/- is not derived from the optical line and is suspect. txfifoslipi when ?1? indicates that ther e has been an underflow or overflow in the tx_sync_fifo when the local system side loopback mode is enabled. bit type function default bit 15 r/w enable0[15] 0 bit 14 r/w enable0[14] 0 bit 13 r/w enable0[13] 0 bit 12 r/w enable0[12] 0 bit 11 r/w enable0[11] 0 bit 10 r/w enable0[10] 0 bit 9 r/w enable0[9] 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 117 document no.: pmc-2001304, issue 7 bit type function default bit 8 r/w enable0[8] 0 bit 7 r/w enable0[7] 0 bit 6 r/w enable0[6] 0 bit 5 r/w enable0[5] 0 bit 4 r/w enable0[4] 0 bit 3 r/w enable0[3] 0 bit 2 r/w enable0[2] 0 bit 1 r/w enable0[1] 0 bit 0 r/w enable0[0] 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 118 document no.: pmc-2001304, issue 7 register 0x0107h:xsbi interrupt enable2 bit type function default bit 15 r/w enable2[15] 0 bit 14 r/w enable2[14] 0 bit 13 r/w enable2[13] 0 bit 12 r/w enable2[12] 0 bit 11 r/w enable2[11] 0 bit 10 r/w enable2[10] 0 bit 9 r/w enable2[9] 0 bit 8 r/w enable2[8] 0 bit 7 r/w enable2[7] 0 bit 6 r/w enable2[6] 0 bit 5 r/w enable2[5] 0 bit 4 r/w enable2[4] 0 bit 3 r/w enable2[3] 0 bit 2 r/w enable2[2] 0 bit 1 r/w enable2[1] 0 bit 0 r/w enable2[0] 0 enable2[15:0] when ?1?, the corresponding rxfifoslipi interrupt will assert the int pin when interrupts are enabled. when ?0?, the rxfifoslipi [0-15] interrupt will have no effect on the interrupt pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 119 document no.: pmc-2001304, issue 7 register 0x0108h:xsbi interrupt enable3 bit type function default bit 15 r/w unused x:high bit 14 r/w unused x:high bit 13 r/w unused x:high bit 12 r/w unused x:high bit 11 r/w unused x:high bit 10 r/w unused x:high bit 9 r/w unused x:high bit 8 r/w unused x:high bit 7 r/w unused x:high bit 6 r/w unused x:high bit 5 r/w unused x:high bit 4 r/w unused x:high bit 3 r/w unused x:high bit 2 r/w enable3[2] 0 bit 1 r/w enable3[1] 0 bit 0 r/w enable3[0] 0 enable3[0] when ?1?, phase_erri interrupt will assert the int pin when interrupts are enabled. when ?0?, the phase_erri interrupt will have no effect on the interrupt pin. enable3[1] when ?1?, sync_erri interrupt will assert th e int pin when interrupts are enabled. when ?0?, the sync_erri interrupt will have no effect on the interrupt pin. enable3[0] when ?1?, txfifoslipi interrupt will assert th e int pin when interrupts are enabled. when ?0?, the txfifoslipi interrupt will have no effect on the interrupt pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 120 document no.: pmc-2001304, issue 7 register 0x0109h:xsbi rxoolv bit type function default bit 15 r rxoolv15 0 bit 14 r rxoolv14 0 bit 13 r rxoolv13 0 bit 12 r rxoolv12 0 bit 11 r rxoolv11 0 bit 10 r rxlock10 0 bit 9 r rxoolv9 0 bit 8 r rxoolv8 0 bit 7 r rxoolv7 0 bit 6 r rxoolv6 0 bit 5 r rxoolv5 0 bit 4 r rxoolv4 0 bit 3 r rxoolv3 0 bit 2 r rxoolv2 0 bit 1 r rxoolv1 0 bit 0 r rxoolv0 0 rxoolv0 ? rxoolv15 the out of lock status (rxoolv) reflects the state of the mpgm monitor?s state machine. when rxoolv [0-15] is set high, th e mpgm [0-15] monitor state machine is in the out of locked state. when oolv is low, the monitor is in lock state.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 121 document no.: pmc-2001304, issue 7 register 0x010ah:xsbi analog debug register bit type function default bit 15 r/w unused x:high bit 14 r/w unused x:high bit 13 r/w unused x:high bit 12 r/w unused x:high bit 11 r/w unused x:high bit 10 r/w unused x:high bit 9 r/w tin[3] 0 bit 8 r/w tin[2] 0 bit 7 r/w tin[1] 0 bit 6 r/w tin[0] 0 bit 5 r/w atms[5] 0 bit 4 r/w atms[4] 0 bit 3 r/w atms[3] 0 bit 2 r/w atms[2] 0 bit 1 r/w atms[1] 0 bit 0 r/w atms[0] 0 at m s [ 5 : 0 ] analog test mode select bus atms[5:0] is used to select the block to be tested in the oifs abc in analog test mode. tin[3:0] tin[3:0] is used to select the test points in the block selected by atms[5:0] in the oifs abc in analog test mode.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 122 document no.: pmc-2001304, issue 7 register 0x2040h:rxxg configuration 1 bit type function default bit 15 r/w rxen 0 bit 14 r/w rocf 0:high bit 13 r/w pad_strip 0:high bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w purep 1 bit 9 r/w longp 0 bit 8 r/w parf 0 bit 7 r/w flchk 0 bit 6 r/w reserved 0 bit 5 r/w pass_ctrl 0 bit 4 r/w rx_contig 1 bit 3 r/w crc_strip 0 bit 2 r/w reserved 1 bit 1 r/w reserved 0 bit 0 r/w reserved 0 rxen when ?1?, receive packet parsing and transfer is enabled. when ?0?, no packet parsing will be initiated, but a packet reception in pr ogress will be completed. rxxg should be configured before writing this bit as ?1?. rocf respond to oversize control frames. when ?1?, the rxxg will pause when an oversize (>=64) byte pause frame is received. wh en ?0? the rxxg will only pause when 64 byte pause frames are received. pad_strip when ?1?, the rxxg will pad strip all non-erro red and non-vlan tagged packets received. pad stripping means that all frames will be tr uncated to the length field specified in the frame. when ?0?, pad stripping will be disable d. note that if crc_strip must be set to ?1? when pad_strip = ?1?. behavior is not defined if crc_strip is ?0? and pad_strip = ?1?. note: if frame length check is enabled and pad st rip is also enabled, packets padded up to 64 bytes are the only padded packets that will not generate a frame length check error. vlan tagged frames are not pad stripped.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 123 document no.: pmc-2001304, issue 7 reserved this bit must be programmed to 0. operation is not guaranteed otherwise. purep pure preamble. set this bit to cause rxxg to ch eck the contents of the preamble field of the packet, ensuring a data pattern of 0x55. clear this bit if no preamble checking is desired. longp long preamble. set this bit to permit recepti on of packets with any number of preamble. clear this bit to cause rxxg to discard p ackets with >11 bytes of preamble. parf pass all receive frames. when this bit is ?0?, rxxg will process pause control frames, extracting the pause parameter from the packet to transfer to the txxg and then discard the packet. when this bit is ?1?, rxxg w ill not process pause control frames and will forward the packet (provided it is not filtered for error reasons). note: if parf= 1; the forwarding of pause frames only relies on the mac control frame type of 0x8808 and the pause opcode of 0x0001 and no errors associated with the received frame. flchk frame length check. when this bit is ?1?, rxxg will compare the actual frame length against the value contained in the type/length field of the mac header. this check is only done if the type/length field is in the range (0-1518). if a length mismatch occurs, the frame will be discarded. when this bit is ?0?, this check is not performed. note: if frame length check is enabled and pad strip is also enabled, packets padded up to 64 bytes are the only padded packets that w ill not generate a frame length check error. also vlan tagged frames will not generate a frame length check error. pass_ctrl pass mac control frames. when this bit is ?1?, rxxg will forward mac control non- pause frames to the system in terface. when this bit is ?0 ?, rxxg will filter these frames. mac control pause frame processing and filtering is determined by parf bit.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 124 document no.: pmc-2001304, issue 7 rx_contig receive packet contiguous. this configuration register bit must always be sent to 0 on initialization. operation is not guaranteed if this bit is set to 1. crc_strip crc strip register bit. when this bit is ?1?, rxxg will strip the crc from the packet. when this bit is ?0?, the packet is forwarded through rxxg with the crc appended
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 125 document no.: pmc-2001304, issue 7 register 0x2042h:rxxg configuration 3 bit type function default bit 15 r/w min_lerre 0 bit 14 r/w max_lerre 0 bit 13 r/w odd_aligne 0 bit 12 r/w line_erre 0 bit 11 r/w reserved 0 bit 10 r/w rx_ovre 0 bit 9 r/w adr_filtere 0 r/w err_detecte 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w prmb_erre 0 bit 4 r unused x:high bit 3 r unused x:high bit 2 r unused x:high bit 1 r unused x:high bit 0 r unused x:high min_lerre the min_lerre bit enables the generation of an interrupt due to a packet sourced from the line interface being less that the minimum frame size of 64 bytes. the frame size does not include preamble/ sfd bytes or prepended fra me delineation headers. it just covers the mac frame contents including crc. max_lerre the max_lerre bit enables the generation of an interrupt due to a packet sourced from the line interface exceeding the maximum frame size programmed in the maximum frame length register. the frame size does not include preamble/ sfd bytes or prepended frame delineation headers. it just covers the mac frame contents including crc. odd_aligne the odd_aligne bit enables the generation of an interrupt due to a packet sourced from the line interface not starting on a 32-bit alignmen t. this is in support of the requirements for the 64b/66b pcs framing schemes, which are co nstrained to 32-bit start alignment. this interrupt indicates a possible framing error.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 126 document no.: pmc-2001304, issue 7 line_erre the line_erre bit enables the generation of an interrupt due to any line interface errors. see the description of line_erri in the rxxg interrupt register for a description of errors. rx_ovre the rx_ovre bit enables the generation of an interrupt due to a receive overrun causes by upstream blockage subsequently causing an overrun of the rxxg internal fifo. adr_filtere the adr_filtere bit enables the generation of an interrupt whenever a packet is filtered by rxxg, due to mac address filter functions. err_detecte this bit is set when a protocol error( crc, fr ame length, range check) is seen in a packet. the packet will be filtered by rxxg when pass_ errors = '0' and the packet is less than the programmable fifo threshold value, otherw ise the packet is forwarded and marked as errored prmb_erre prmb_erre enables the prmb_erri bit generating an interrupt output (int). prmb_erri is set when a packet is received that violates the preamble expected. the expected preamble is dependent on purep a nd longp in rxxg configuration register 1. if prmb_erre is ?1? in rxxg configuration 3 register, an interrupt will also be generated (int output asserted).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 127 document no.: pmc-2001304, issue 7 register 0x2043h:rxxg interrupt bit type function default bit 15 r min_lerri 0 bit 14 r max_lerri 0 bit 13 r odd_aligni 0 bit 12 r line_erri 0 bit 11 r reserved 0 bit 10 r rx_ovri 0 bit 9 r adr_filteri 0 bit 8 r err_detecti 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r prmb_erri 0 bit 4 r unused x:high bit 3 r unused x:high bit 2 r unused x:high bit 1 r unused x:high bit 0 r unused x:high min_lerri the min_lerri bit will be set when the pack et sourced from the line interface is less than the legal minimum of 64 bytes. the frame size does not include preamble/ sfd bytes or prepended frame delineation headers. it ju st covers the mac frame contents including crc. if min_lerre is ?1? in rxxg configuratio n 3 register, an interrupt will also be generated (int output asserted). max_lerri the max_lerri bit will be set when the p acket sourced from the line interface exceeds the maximum frame size programmed in the maximum frame length register. the frame size does not include preamble/ sfd bytes or prepended frame delineation headers. if max_lerre is ?1? in rxxg configuration 3 regi ster, an interrupt will also be generated (int output asserted) odd_aligni the odd_aligni bit is set when the packet sourced from the line interface does not start on an even 32-bit alignment. this is in support of the requirements for xaui and 64b/66b pcs framing schemes which are constrained to this start alignment. rxxg will accept frames on any byte alignment. this interrupt is just an indication of a possible framing error. if odd_aligne is ?1? in rxxg configura tion 3 register, an interrupt will also be generated (int output asserted).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 128 document no.: pmc-2001304, issue 7 line_erri the line_erri bit is set when a line interf ace error is detected. if line_erre is ?1? in rxxg configuration 3 register, an interrupt will also be generate d (int output asserted). failure modes are (1) breakdown in alterna ting sop-eop sequence (2) invalid byte(s) between sop and eop not part of a completely invalid word. (3) r eception of frames less than 14 bytes. rx_ovri the rx_ovri bit is set when a receive overrun is caused by the fifo_full[15:0] inputs being asserted and subsequently causing an overrun of the rxxg internal fifo. if rx_ovre is ?1? in rxxg configuration 3 regi ster, an interrupt will also be generated (int output asserted). adr_filteri the adr_filteri bit is set whenever a packet is filtered by rxxg, due to mac address filter functions. if adr_filtere is ?1? in rxxg configuration 3 register, an interrupt will also be generated (int output asserted). err_detecti the err_detecti bit is set whenever a packet is filtered by rxxg, due protocol error conditions. if err_detecti is ?1? in rxxg c onfiguration 3 register, an interrupt will also be generated (int output asserted). prmb_erri prmb_erri is set when a packet is received that violates the preamble expected. the expected preamble is dependent on purep a nd longp in rxxg configuration register 1. if prmb_erre is ?1? in rxxg configuration 3 register, an interrupt will also be generated (int output asserted).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 129 document no.: pmc-2001304, issue 7 register 0x2044h:rxxg status bit type function default bit 15 r reserved 0 bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r unused x:high bit 4 r unused x:high bit 3 r unused x:high bit 2 r unused x:high bit 1 r unused x:high bit 0 r unused x:high
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 130 document no.: pmc-2001304, issue 7 register 0x2045h:rxxg maximum frame length bit type function default bit 15 r/w rx_maxfr[15] 0 bit 14 r/w rx_maxfr[14] 0 bit 13 r/w rx_maxfr[13] 0 bit 12 r/w rx_maxfr[12] 0 bit 11 r/w rx_maxfr[11] 0 bit 10 r/w rx_maxfr[10] 1 bit 9 r/w rx_maxfr[9] 0 bit 8 r/w rx_maxfr[8] 1 bit 7 r/w rx_maxfr[7] 1 bit 6 r/w rx_maxfr[6] 1 bit 5 r/w rx_maxfr[5] 1 bit 4 r/w rx_maxfr[4] 0 bit 3 r/w rx_maxfr[3] 1 bit 2 r/w rx_maxfr[2] 1 bit 1 r/w rx_maxfr[1] 1 bit 0 r/w rx_maxfr[0] 0 rx_maxfr[15:0] this field resets to 0x05ee, which represents a maximum receive frame of 1518 octets. an untagged maximum size ethernet frame is 1518 oc tets in length. a ta gged frame adds four octets for a total of 1522 octets. if a differ ent maximum length restriction is desired, program this 16-bit field. frames which exceed this length will be truncated to match the specified length. note: this does not include the length of preamble/ sfd bytes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 131 document no.: pmc-2001304, issue 7 register 0x2046h:rxxg sa[15:0] ? station address bit type function default bit 15 r/w sa[15] 0 bit 14 r/w sa [14] 0 bit 13 r/w sa [13] 0 bit 12 r/w sa [12] 0 bit 11 r/w sa [11] 0 bit 10 r/w sa [10] 0 bit 9 r/w sa [9] 0 bit 8 r/w sa [8] 0 bit 7 r/w sa [7] 0 bit 6 r/w sa [6] 0 bit 5 r/w sa [5] 0 bit 4 r/w sa [4] 0 bit 3 r/w sa [3] 0 bit 2 r/w sa [2] 0 bit 1 r/w sa[1] 0 bit 0 r/w sa[0] 0 sa[15:0] station address low word. mac control pause frames may be addressed to the well- known multicast address assigned for this purpose, or to the station address directly i.e. sa[47 :0]. the mac control sublayer expects either the multicast address or the station address as criteria to respond to the pause frame received.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 132 document no.: pmc-2001304, issue 7 register 0x2047h:rxxg sa[31:16] ? station address bit type function default bit 15 r/w sa[31] 0 bit 14 r/w sa [30] 0 bit 13 r/w sa [29] 0 bit 12 r/w sa [28] 0 bit 11 r/w sa [27] 0 bit 10 r/w sa [26] 0 bit 9 r/w sa [25] 0 bit 8 r/w sa [24] 0 bit 7 r/w sa [23] 0 bit 6 r/w sa [22] 0 bit 5 r/w sa [21] 0 bit 4 r/w sa [20] 0 bit 3 r/w sa [19] 0 bit 2 r/w sa [18] 0 bit 1 r/w sa[17] 0 bit 0 r/w sa[16] 0 sa[31:16] station address mid word. mac control pause frames may be addressed to the well- known multicast address assigned for this purpose, or to the station address directly i.e. sa[47 :0] . the mac control sublayer expects either the multicast address or the station address as criteria to respond to the pause frame received.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 133 document no.: pmc-2001304, issue 7 register 0x2048h:rxxg sa[47:32] ? station address bit type function default bit 15 r/w sa[47] 0 bit 14 r/w sa [46] 0 bit 13 r/w sa [45] 0 bit 12 r/w sa [44] 0 bit 11 r/w sa [43] 0 bit 10 r/w sa [42] 0 bit 9 r/w sa [41] 0 bit 8 r/w sa [40] 0 bit 7 r/w sa [39] 0 bit 6 r/w sa [38] 0 bit 5 r/w sa [37] 0 bit 4 r/w sa [36] 0 bit 3 r/w sa [35] 0 bit 2 r/w sa [34] 0 bit 1 r/w sa[33] 0 bit 0 r/w sa[32] 0 sa[47:32] station address high word. mac control p ause frames may be addressed to the well- known multicast address assigned for this purpose, or to the station address directly i.e. sa[47 :0] . the mac control sublayer expects either the multicast address or the station address as criteria to respond to the pause frame received.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 134 document no.: pmc-2001304, issue 7 register 0x2049h:rxxg receive fifo threshold bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r unused x:high bit 4 r unused x:high bit 3 r unused x:high bit 2 r/w cut_thru_thres_ sel[2] 1 bit 1 r/w cut_thru_thres_ sel[1] 0 bit 0 r/w cut_thru_thres_ sel[0] 1 cut_thru_thres_sel[2:0]: cut_thru_thres_sel pkt_fifo_threshold 0 8 (64 bytes) 1 64 (512 bytes) 2 128 (1024 bytes) 3 192 (1536 bytes) 4 224 (1792 bytes) 5 eop write triggers reading from pkt fifo.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 135 document no.: pmc-2001304, issue 7 cut-thru threshold select, sets the forwarding th reshold in the internal receive fifo for initiating packet transfer to the system fifo interface. default is 0x5 or 255 x 64-bit entries or 2040 bytes (+/-7 bytes). this defines a stor e-and-forward mode of operation. this mode of operation can be used only when all packet s received are expected to be less than or equal to 2000. packets greater than 2000 will be truncated (to prevent fifo filling) and marked as errored. to configure rxxg for cu t-through mode, program cut_thru_thres_sel to 0,1, 2, 3, or 4. increasing the threshold value, increases the errored packet size rxxg can filter. this mode of operation can be u sed where packets greater than the fifo size (~2000 bytes) are expected, i.e. jumbo packets, but errored packets less than the threshold value are to be filtered. if a packet breaks th e cut-through threshold, rxxg begins to read the packet out. as rxxg can only determine if a packet is errored after the eop is received, it is not possible to filter this pack et. since each word in the ram can occupy 8 bytes of data, packets that are under the mini mum size to fill the threshold can only be filtered by rxxg. for example, cut_thru_sel = 4 => 224 words => 1 byte on first + 222 x 8 bytes + 2 x 8 bytes (latency) - 8 bytes (possible line gap inside a packet, i.e. dead-band ------------------ ---------- --------- 1786 byte packet hence, the absolute maximum size packet rxxg can guarantee to filter, when cut_thru_sel = 4, is a 1785 byte packet. depending on the offset of the sop in the ram, i.e. is the sop in the msbyte of th e ram, the rxxg will filter or forward packets between 1786 bytes and 1808 (224x8) bytes. below is a table illustrating the acceptable packet sizes for filtering based on the cut_thru_sel value. table 14 cut_thru_thres packet sizes cut_thru_sel 0 1 2 3 4 5 words to threshold 8 64 128 192 224 n/a guaranteed maximum size packet rxxg will filter 57 505 1017 1529 1785 1992 filter or forward packets in this range 58 - 80 ?506 - 528 ?1018 - 1040 ?1530 - 1552 ?1786 - 1808 n/a guaranteed minimum size packet rxxg will not filter >80 >528 >1041 >1552 >1808 n/a
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 136 document no.: pmc-2001304, issue 7 a cut_thru_thres_sel value of 5 will mean that the pkt fifo will never go into cut_thru mode, i.e. no support for jumbo packets in rxxg. when the packet size goes over 2040 bytes the pkt fifo will overrun.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 137 document no.: pmc-2001304, issue 7 register 0x204ah:rxxg exact match address 0 low word bit type function default bit 15 r/w adr_match0[15] 0 bit 14 r/w adr_match0 [14] 0 bit 13 r/w adr_match0 [13] 0 bit 12 r/w adr_match0 [12] 0 bit 11 r/w adr_match0 [11] 0 bit 10 r/w adr_match0 [10] 0 bit 9 r/w adr_match0 [9] 0 bit 8 r/w adr_match0 [8] 0 bit 7 r/w adr_match0 [7] 0 bit 6 r/w adr_match0 [6] 0 bit 5 r/w adr_match0 [5] 0 bit 4 r/w adr_match0 [4] 0 bit 3 r/w adr_match0 [3] 0 bit 2 r/w adr_match0 [2] 0 bit 1 r/w adr_match0 [1] 0 bit 0 r/w adr_match0 [0] 0 adr_match0[15:0] the exact match address 0 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 138 document no.: pmc-2001304, issue 7 register 0x204bh:rxxg exact match address 0 mid word bit type function default bit 15 r/w adr_match0[31] 0 bit 14 r/w adr_match0 [30] 0 bit 13 r/w adr_match0 [29] 0 bit 12 r/w adr_match0 [28] 0 bit 11 r/w adr_match0 [27] 0 bit 10 r/w adr_match0 [26] 0 bit 9 r/w adr_match0 [25 0 bit 8 r/w adr_match0 [24] 0 bit 7 r/w adr_match0 [23] 0 bit 6 r/w adr_match0 [22] 0 bit 5 r/w adr_match0 [21] 0 bit 4 r/w adr_match0 [20] 0 bit 3 r/w adr_match0 [19] 0 bit 2 r/w adr_match0 [18] 0 bit 1 r/w adr_match0 [17] 0 bit 0 r/w adr_match0 [16] 0 adr_match0[31:16] the exact match address 0 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 139 document no.: pmc-2001304, issue 7 register 0x204ch:rxxg exact match address 0 high word bit type function default bit 15 r/w adr_match0[47] 0 bit 14 r/w adr_match0 [46] 0 bit 13 r/w adr_match0 [45] 0 bit 12 r/w adr_match0 [44] 0 bit 11 r/w adr_match0 [43] 0 bit 10 r/w adr_match0 [42] 0 bit 9 r/w adr_match0 [41] 0 bit 8 r/w adr_match0 [40] 0 bit 7 r/w adr_match0 [39] 0 bit 6 r/w adr_match0 [38] 0 bit 5 r/w adr_match0 [37] 0 bit 4 r/w adr_match0 [36] 0 bit 3 r/w adr_match0 [35] 0 bit 2 r/w adr_match0 [34] 0 bit 1 r/w adr_match0 [33] 0 bit 0 r/w adr_match0 [32] 0 adr_match0[47:32] the exact match address 0 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 140 document no.: pmc-2001304, issue 7 register 0x204dh:rxxg exact match address 1 low word bit type function default bit 15 r/w adr_match1[15] 0 bit 14 r/w adr_match1 [14] 0 bit 13 r/w adr_match1 [13] 0 bit 12 r/w adr_match1 [12] 0 bit 11 r/w adr_match1 [11] 0 bit 10 r/w adr_match1 [10] 0 bit 9 r/w adr_match1 [9] 0 bit 8 r/w adr_match1 [8] 0 bit 7 r/w adr_match1 [7] 0 bit 6 r/w adr_match1 [6] 0 bit 5 r/w adr_match1 [5] 0 bit 4 r/w adr_match1 [4] 0 bit 3 r/w adr_match1 [3] 0 bit 2 r/w adr_match1 [2] 0 bit 1 r/w adr_match1 [1] 0 bit 0 r/w adr_match1 [0] 0 adr_match1[15:0] the exact match address 1 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 141 document no.: pmc-2001304, issue 7 register 0x204eh: rxxg exact match address 1 mid word bit type function default bit 15 r/w adr_match1[31] 0 bit 14 r/w adr_match1 [30] 0 bit 13 r/w adr_match1 [29] 0 bit 12 r/w adr_match1 [28] 0 bit 11 r/w adr_match1 [27] 0 bit 10 r/w adr_match1 [26] 0 bit 9 r/w adr_match1 [25] 0 bit 8 r/w adr_match1 [24] 0 bit 7 r/w adr_match1 [23] 0 bit 6 r/w adr_match1 [22] 0 bit 5 r/w adr_match1 [21] 0 bit 4 r/w adr_match1 [20] 0 bit 3 r/w adr_match1 [19] 0 bit 2 r/w adr_match1 [18] 0 bit 1 r/w adr_match1 [17] 0 bit 0 r/w adr_match1 [16] 0 adr_match1[31:16] the exact match address 1 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 142 document no.: pmc-2001304, issue 7 register 0x204fh:rxxg exact match address 1 high word bit type function default bit 15 r/w adr_match1[47] 0 bit 14 r/w adr_match1 [46] 0 bit 13 r/w adr_match1 [45] 0 bit 12 r/w adr_match1 [44] 0 bit 11 r/w adr_match1 [43] 0 bit 10 r/w adr_match1 [42] 0 bit 9 r/w adr_match1 [41] 0 bit 8 r/w adr_match1 [40] 0 bit 7 r/w adr_match1 [39] 0 bit 6 r/w adr_match1 [38] 0 bit 5 r/w adr_match1 [37] 0 bit 4 r/w adr_match1 [36] 0 bit 3 r/w adr_match1 [35] 0 bit 2 r/w adr_match1 [34] 0 bit 1 r/w adr_match1 [33] 0 bit 0 r/w adr_match1 [32] 0 adr_match1[47:32] the exact match address 1 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 143 document no.: pmc-2001304, issue 7 register 0x2050h:rxxg exact match address 2 low word bit type function default bit 15 r/w adr_match2[15] 0 bit 14 r/w adr_match2 [14] 0 bit 13 r/w adr_match2 [13] 0 bit 12 r/w adr_match2 [12] 0 bit 11 r/w adr_match2 [11] 0 bit 10 r/w adr_match2 [10] 0 bit 9 r/w adr_match2 [9] 0 bit 8 r/w adr_match2 [8] 0 bit 7 r/w adr_match2 [7] 0 bit 6 r/w adr_match2 [6] 0 bit 5 r/w adr_match2 [5] 0 bit 4 r/w adr_match2 [4] 0 bit 3 r/w adr_match2 [3] 0 bit 2 r/w adr_match2 [2] 0 bit 1 r/w adr_match2 [1] 0 bit 0 r/w adr_match2 [0] 0 adr_match2[15:0] the exact match address 2 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 144 document no.: pmc-2001304, issue 7 register 0x2051h:rxxg exact match address 2 mid word bit type function default bit 15 r/w adr_match2[31] 0 bit 14 r/w adr_match2 [30] 0 bit 13 r/w adr_match2 [29] 0 bit 12 r/w adr_match2 [28] 0 bit 11 r/w adr_match2 [27] 0 bit 10 r/w adr_match2 [26] 0 bit 9 r/w adr_match2 [25] 0 bit 8 r/w adr_match2 [24] 0 bit 7 r/w adr_match2 [23] 0 bit 6 r/w adr_match2 [22] 0 bit 5 r/w adr_match2 [21] 0 bit 4 r/w adr_match2 [20] 0 bit 3 r/w adr_match2 [19] 0 bit 2 r/w adr_match2 [18] 0 bit 1 r/w adr_match2 [17] 0 bit 0 r/w adr_match2 [16] 0 adr_match2[31:16] the exact match address 2 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 145 document no.: pmc-2001304, issue 7 register 0x2052h:rxxg exact match address 2 high word bit type function default bit 15 r/w adr_match2[47] 0 bit 14 r/w adr_match2 [46] 0 bit 13 r/w adr_match2 [45] 0 bit 12 r/w adr_match2 [44] 0 bit 11 r/w adr_match2 [43] 0 bit 10 r/w adr_match2 [42] 0 bit 9 r/w adr_match2 [41] 0 bit 8 r/w adr_match2 [40] 0 bit 7 r/w adr_match2[39] 0 bit 6 r/w adr_match2 [38] 0 bit 5 r/w adr_match2 [37] 0 bit 4 r/w adr_match2 [36] 0 bit 3 r/w adr_match2 [35] 0 bit 2 r/w adr_match2 [34] 0 bit 1 r/w adr_match2 [33] 0 bit 0 r/w adr_match2 [32] 0 adr_match2[47:32] the exact match address 2 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 146 document no.: pmc-2001304, issue 7 register 0x2053h:rxxg exact match address 3 low word bit type function default bit 15 r/w adr_match3[15] 0 bit 14 r/w adr_match3 [14] 0 bit 13 r/w adr_match3 [13] 0 bit 12 r/w adr_match3 [12] 0 bit 11 r/w adr_match3 [11] 0 bit 10 r/w adr_match3 [10] 0 bit 9 r/w adr_match3 [9] 0 bit 8 r/w adr_match3 [8] 0 bit 7 r/w adr_match3 [7] 0 bit 6 r/w adr_match3 [6] 0 bit 5 r/w adr_match3 [5] 0 bit 4 r/w adr_match3 [4] 0 bit 3 r/w adr_match3 [3] 0 bit 2 r/w adr_match3 [2] 0 bit 1 r/w adr_match3 [1] 0 bit 0 r/w adr_match3 [0] 0 adr_match3[15:0] the exact match address 3 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 147 document no.: pmc-2001304, issue 7 register 0x2054h:rxxg exact match address 3 mid word bit type function default bit 15 r/w adr_match3[31] 0 bit 14 r/w adr_match3 [30] 0 bit 13 r/w adr_match3 [29] 0 bit 12 r/w adr_match3 [28] 0 bit 11 r/w adr_match3 [27] 0 bit 10 r/w adr_match3 [26] 0 bit 9 r/w adr_match3 [25] 0 bit 8 r/w adr_match3 [24] 0 bit 7 r/w adr_match3 [23] 0 bit 6 r/w adr_match3 [22] 0 bit 5 r/w adr_match3 [21] 0 bit 4 r/w adr_match3 [20] 0 bit 3 r/w adr_match3 [19] 0 bit 2 r/w adr_match3 [18] 0 bit 1 r/w adr_match3 [17] 0 bit 0 r/w adr_match3 [16] 0 adr_match3[31:16] the exact match address 3 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 148 document no.: pmc-2001304, issue 7 register 0x2055h:rxxg exact match address 3 high word bit type function default bit 15 r/w adr_match3[47] 0 bit 14 r/w adr_match3 [46] 0 bit 13 r/w adr_match3 [45] 0 bit 12 r/w adr_match3 [44] 0 bit 11 r/w adr_match3 [43] 0 bit 10 r/w adr_match3 [42] 0 bit 9 r/w adr_match3 [41] 0 bit 8 r/w adr_match3 [40] 0 bit 7 r/w adr_match3 [39] 0 bit 6 r/w adr_match3 [38] 0 bit 5 r/w adr_match3 [37] 0 bit 4 r/w adr_match3 [36] 0 bit 3 r/w adr_match3 [35] 0 bit 2 r/w adr_match3 [34] 0 bit 1 r/w adr_match3 [33] 0 bit 0 r/w adr_match3 [32] 0 adr_match3[47:32] the exact match address 3 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 149 document no.: pmc-2001304, issue 7 register 0x2056h:rxxg exact match address 4 low word bit type function default bit 15 r/w adr_match4[15] 0 bit 14 r/w adr_match4 [14] 0 bit 13 r/w adr_match4 [13] 0 bit 12 r/w adr_match4 [12] 0 bit 11 r/w adr_match4 [11] 0 bit 10 r/w adr_match4 [10] 0 bit 9 r/w adr_match4 [9] 0 bit 8 r/w adr_match4 [8] 0 bit 7 r/w adr_match4 [7] 0 bit 6 r/w adr_match4 [6] 0 bit 5 r/w adr_match4 [5] 0 bit 4 r/w adr_match4 [4] 0 bit 3 r/w adr_match4 [3] 0 bit 2 r/w adr_match4 [2] 0 bit 1 r/w adr_match4 [1] 0 bit 0 r/w adr_match4 [0] 0 adr_match4[15:0] the exact match address 4 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 150 document no.: pmc-2001304, issue 7 register 0x2057h:rxxg exact match address 4 mid word bit type function default bit 15 r/w adr_match4[31] 0 bit 14 r/w adr_match4 [30] 0 bit 13 r/w adr_match4 [29] 0 bit 12 r/w adr_match4 [28] 0 bit 11 r/w adr_match4 [27] 0 bit 10 r/w adr_match4 [26] 0 bit 9 r/w adr_match4 [25] 0 bit 8 r/w adr_match4 [24] 0 bit 7 r/w adr_match4 [23] 0 bit 6 r/w adr_match4 [22] 0 bit 5 r/w adr_match4 [21] 0 bit 4 r/w adr_match4 [20] 0 bit 3 r/w adr_match4 [19] 0 bit 2 r/w adr_match4 [18] 0 bit 1 r/w adr_match4 [17] 0 bit 0 r/w adr_match4 [16] 0 adr_match4[31:16] the exact match address 4 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 151 document no.: pmc-2001304, issue 7 register 0x2058h:rxxg exact match address 4 high word bit type function default bit 15 r/w adr_match4[47] 0 bit 14 r/w adr_match4 [46] 0 bit 13 r/w adr_match4 [45] 0 bit 12 r/w adr_match4 [44] 0 bit 11 r/w adr_match4 [43] 0 bit 10 r/w adr_match4 [42] 0 bit 9 r/w adr_match4 [41] 0 bit 8 r/w adr_match4 [40] 0 bit 7 r/w adr_match4 [39] 0 bit 6 r/w adr_match4 [38] 0 bit 5 r/w adr_match4 [37] 0 bit 4 r/w adr_match4 [36] 0 bit 3 r/w adr_match4 [35] 0 bit 2 r/w adr_match4 [34] 0 bit 1 r/w adr_match4 [33] 0 bit 0 r/w adr_match4 [32] 0 adr_match4[47:32] the exact match address 4 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 152 document no.: pmc-2001304, issue 7 register 0x2059h:rxxg exact match address 5 low word bit type function default bit 15 r/w adr_match5[15] 0 bit 14 r/w adr_match5 [14] 0 bit 13 r/w adr_match5 [13] 0 bit 12 r/w adr_match5 [12] 0 bit 11 r/w adr_match5 [11] 0 bit 10 r/w adr_match5 [10] 0 bit 9 r/w adr_match5 [9] 0 bit 8 r/w adr_match5 [8] 0 bit 7 r/w adr_match5 [7] 0 bit 6 r/w adr_match5 [6] 0 bit 5 r/w adr_match5 [5] 0 bit 4 r/w adr_match5 [4] 0 bit 3 r/w adr_match5 [3] 0 bit 2 r/w adr_match5 [2] 0 bit 1 r/w adr_match5 [1] 0 bit 0 r/w adr_match5 [0] 0 adr_match5[15:0] the exact match address 5 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 153 document no.: pmc-2001304, issue 7 register 0x205ah:rxxg exact match address 5 mid word bit type function default bit 15 r/w adr_match5[31] 0 bit 14 r/w adr_match5 [30] 0 bit 13 r/w adr_match5 [29] 0 bit 12 r/w adr_match5 [28] 0 bit 11 r/w adr_match5 [27] 0 bit 10 r/w adr_match5 [26] 0 bit 9 r/w adr_match5 [25] 0 bit 8 r/w adr_match5 [24] 0 bit 7 r/w adr_match5 [23] 0 bit 6 r/w adr_match5 [22] 0 bit 5 r/w adr_match5 [21] 0 bit 4 r/w adr_match5 [20] 0 bit 3 r/w adr_match5 [19] 0 bit 2 r/w adr_match5 [18] 0 bit 1 r/w adr_match5 [17] 0 bit 0 r/w adr_match5 [16] 0 adr_match5[31:16] the exact match address 5 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 154 document no.: pmc-2001304, issue 7 register 0x205bh:rxxg exact match address 5 high word bit type function default bit 15 r/w adr_match5[47] 0 bit 14 r/w adr_match5 [46] 0 bit 13 r/w adr_match5 [45] 0 bit 12 r/w adr_match5 [44] 0 bit 11 r/w adr_match5 [43] 0 bit 10 r/w adr_match5 [42] 0 bit 9 r/w adr_match5 [41] 0 bit 8 r/w adr_match5 [40] 0 bit 7 r/w adr_match5 [39] 0 bit 6 r/w adr_match5 [38] 0 bit 5 r/w adr_match5 [37] 0 bit 4 r/w adr_match5 [36] 0 bit 3 r/w adr_match5 [35] 0 bit 2 r/w adr_match5 [34] 0 bit 1 r/w adr_match5 [33] 0 bit 0 r/w adr_match5 [32] 0 adr_match5[47:32] the exact match address 5 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 155 document no.: pmc-2001304, issue 7 register 0x205ch:rxxg exact match address 6 low word bit type function default bit 15 r/w adr_match6[15] 0 bit 14 r/w adr_match6 [14] 0 bit 13 r/w adr_match6 [13] 0 bit 12 r/w adr_match6 [12] 0 bit 11 r/w adr_match6 [11] 0 bit 10 r/w adr_match6 [10] 0 bit 9 r/w adr_match6 [9] 0 bit 8 r/w adr_match6 [8] 0 bit 7 r/w adr_match6 [7] 0 bit 6 r/w adr_match6 [6] 0 bit 5 r/w adr_match6 [5] 0 bit 4 r/w adr_match6 [4] 0 bit 3 r/w adr_match6 [3] 0 bit 2 r/w adr_match6 [2] 0 bit 1 r/w adr_match6 [1] 0 bit 0 r/w adr_match6 [0] 0 adr_match6[15:0] the exact match address 6 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 156 document no.: pmc-2001304, issue 7 register 0x205dh:rxxg exact match address 6 mid word bit type function default bit 15 r/w adr_match6[31] 0 bit 14 r/w adr_match6 [30] 0 bit 13 r/w adr_match6 [29] 0 bit 12 r/w adr_match6 [28] 0 bit 11 r/w adr_match6 [27] 0 bit 10 r/w adr_match6 [26] 0 bit 9 r/w adr_match6 [25] 0 bit 8 r/w adr_match6 [24] 0 bit 7 r/w adr_match6 [23] 0 bit 6 r/w adr_match6 [22] 0 bit 5 r/w adr_match6 [21] 0 bit 4 r/w adr_match6 [20] 0 bit 3 r/w adr_match6 [19] 0 bit 2 r/w adr_match6 [18] 0 bit 1 r/w adr_match6 [17] 0 bit 0 r/w adr_match6 [16] 0 adr_match6[31:16] the exact match address 6 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 157 document no.: pmc-2001304, issue 7 register 0x205eh:rxxg exact match address 6 high word bit type function default bit 15 r/w adr_match6[47] 0 bit 14 r/w adr_match6 [46] 0 bit 13 r/w adr_match6 [45] 0 bit 12 r/w adr_match6 [44] 0 bit 11 r/w adr_match6 [43] 0 bit 10 r/w adr_match6 [42] 0 bit 9 r/w adr_match6 [41] 0 bit 8 r/w adr_match6 [40] 0 bit 7 r/w adr_match6 [39] 0 bit 6 r/w adr_match6 [38] 0 bit 5 r/w adr_match6 [37] 0 bit 4 r/w adr_match6 [36] 0 bit 3 r/w adr_match6 [35] 0 bit 2 r/w adr_match6 [34] 0 bit 1 r/w adr_match6 [33] 0 bit 0 r/w adr_match6 [32] 0 adr_match6[47:32] the exact match address 6 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 158 document no.: pmc-2001304, issue 7 register 0x205fh: rxxg exact match address 7 low word bit type function default bit 15 r/w adr_match7[15] 0 bit 14 r/w adr_match7 [14] 0 bit 13 r/w adr_match7 [13] 0 bit 12 r/w adr_match7 [12] 0 bit 11 r/w adr_match7 [11] 0 bit 10 r/w adr_match7 [10] 0 bit 9 r/w adr_match7 [9] 0 bit 8 r/w adr_match7 [8] 0 bit 7 r/w adr_match7 [7] 0 bit 6 r/w adr_match7 [6] 0 bit 5 r/w adr_match7 [5] 0 bit 4 r/w adr_match7 [4] 0 bit 3 r/w adr_match7 [3] 0 bit 2 r/w adr_match7 [2] 0 bit 1 r/w adr_match7 [1] 0 bit 0 r/w adr_match7 [0] 0 adr_match7[15:0] the exact match address 7 low word is used for the low word [15:0] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 159 document no.: pmc-2001304, issue 7 register 0x2060h:rxxg exact match address 7 mid word bit type function default bit 15 r/w adr_match7[31] 0 bit 14 r/w adr_match7 [30] 0 bit 13 r/w adr_match7 [29] 0 bit 12 r/w adr_match7 [28] 0 bit 11 r/w adr_match7 [27] 0 bit 10 r/w adr_match7 [26] 0 bit 9 r/w adr_match7 [25] 0 bit 8 r/w adr_match7 [24] 0 bit 7 r/w adr_match7 [23] 0 bit 6 r/w adr_match7 [22] 0 bit 5 r/w adr_match7 [21] 0 bit 4 r/w adr_match7 [20] 0 bit 3 r/w adr_match7 [19] 0 bit 2 r/w adr_match7 [18] 0 bit 1 r/w adr_match7 [17] 0 bit 0 r/w adr_match7 [16] 0 adr_match7[31:16] the exact match address 7 mid word is used for the mid word [31:16] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 160 document no.: pmc-2001304, issue 7 register 0x2061h:rxxg exact match address 7 high word bit type function default bit 15 r/w adr_match7[47] 0 bit 14 r/w adr_match7 [46] 0 bit 13 r/w adr_match7 [45] 0 bit 12 r/w adr_match7 [44] 0 bit 11 r/w adr_match7 [43] 0 bit 10 r/w adr_match7 [42] 0 bit 9 r/w adr_match7 [41] 0 bit 8 r/w adr_match7 [40] 0 bit 7 r/w adr_match7 [39] 0 bit 6 r/w adr_match7 [38] 0 bit 5 r/w adr_match7 [37] 0 bit 4 r/w adr_match7 [36] 0 bit 3 r/w adr_match7 [35] 0 bit 2 r/w adr_match7 [34] 0 bit 1 r/w adr_match7 [33] 0 bit 0 r/w adr_match7 [32] 0 adr_match7[47:32] the exact match address 7 high word is used for the high word [47:32] of the 48-bit mac address that the address filter logic uses to compare on. this register is one of eight separate exact match address registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 161 document no.: pmc-2001304, issue 7 register 0x2062h:rxxg exact match vid 0 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match0[11] 0 bit 10 r/w vid_match0[10] 0 bit 9 r/w vid_match0[9] 0 bit 8 r/w vid_match0[8] 0 bit 7 r/w vid_match0[7] 0 bit 6 r/w vid_match0[6] 0 bit 5 r/w vid_match0[5] 0 bit 4 r/w vid_match0[4] 0 bit 3 r/w vid_match0[3] 0 bit 2 r/w vid_match0[2] 0 bit 1 r/w vid_match0[1] 0 bit 0 r/w vid_match0[0] 0 vid_match0[11:0] the exact match vid 0 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 162 document no.: pmc-2001304, issue 7 register 0x2063h:rxxg exact match vid 1 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match1[11] 0 bit 10 r/w vid_match1[10] 0 bit 9 r/w vid_match1[9] 0 bit 8 r/w vid_match1[8] 0 bit 7 r/w vid_match1[7] 0 bit 6 r/w vid_match1[6] 0 bit 5 r/w vid_match1[5] 0 bit 4 r/w vid_match1[4] 0 bit 3 r/w vid_match1[3] 0 bit 2 r/w vid_match1[2] 0 bit 1 r/w vid_match1[1] 0 bit 0 r/w vid_match1[0] 0 vid_match1[11:0] the exact match vid 1 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 163 document no.: pmc-2001304, issue 7 register 0x2064h:rxxg exact match vid 2 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match2[11] 0 bit 10 r/w vid_match2[10] 0 bit 9 r/w vid_match2[9] 0 bit 8 r/w vid_match2[8] 0 bit 7 r/w vid_match2[7] 0 bit 6 r/w vid_match2[6] 0 bit 5 r/w vid_match2[5] 0 bit 4 r/w vid_match2[4] 0 bit 3 r/w vid_match2[3] 0 bit 2 r/w vid_match2[2] 0 bit 1 r/w vid_match2[1] 0 bit 0 r/w vid_match2[0] 0 vid_match2[11:0] the exact match vid 2 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 164 document no.: pmc-2001304, issue 7 register 0x2065h:rxxg exact match vid 3 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match3[11] 0 bit 10 r/w vid_match3[10] 0 bit 9 r/w vid_match3[9] 0 bit 8 r/w vid_match3[8] 0 bit 7 r/w vid_match3[7] 0 bit 6 r/w vid_match3[6] 0 bit 5 r/w vid_match3[5] 0 bit 4 r/w vid_match3[4] 0 bit 3 r/w vid_match3[3] 0 bit 2 r/w vid_match3[2] 0 bit 1 r/w vid_match3[1] 0 bit 0 r/w vid_match3[0] 0 vid_match3[11:0] the exact match vid 3 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 165 document no.: pmc-2001304, issue 7 register 0x2066h:rxxg exact match vid 4 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match4[11] 0 bit 10 r/w vid_match4[10] 0 bit 9 r/w vid_match4[9] 0 bit 8 r/w vid_match4[8] 0 bit 7 r/w vid_match4[7] 0 bit 6 r/w vid_match4[6] 0 bit 5 r/w vid_match4[5] 0 bit 4 r/w vid_match4[4] 0 bit 3 r/w vid_match4[3] 0 bit 2 r/w vid_match4[2] 0 bit 1 r/w vid_match4[1] 0 bit 0 r/w vid_match4[0] 0 vid_match4[11:0] the exact match vid 4 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 166 document no.: pmc-2001304, issue 7 register 0x2067h:rxxg exact match vid 5 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match5[11] 0 bit 10 r/w vid_match5[10] 0 bit 9 r/w vid_match5[9] 0 bit 8 r/w vid_match5[8] 0 bit 7 r/w vid_match5[7] 0 bit 6 r/w vid_match5[6] 0 bit 5 r/w vid_match5[5] 0 bit 4 r/w vid_match5[4] 0 bit 3 r/w vid_match5[3] 0 bit 2 r/w vid_match5[2] 0 bit 1 r/w vid_match5[1] 0 bit 0 r/w vid_match5[0] 0 vid_match5[11:0] the exact match vid 5 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 167 document no.: pmc-2001304, issue 7 register 0x2068h:rxxg exact match vid 6 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match6[11] 0 bit 10 r/w vid_match6[10] 0 bit 9 r/w vid_match6[9] 0 bit 8 r/w vid_match6[8] 0 bit 7 r/w vid_match6[7] 0 bit 6 r/w vid_match6[6] 0 bit 5 r/w vid_match6[5] 0 bit 4 r/w vid_match6[4] 0 bit 3 r/w vid_match6[3] 0 bit 2 r/w vid_match6[2] 0 bit 1 r/w vid_match6[1] 0 bit 0 r/w vid_match6[0] 0 vid_match6[11:0] the exact match vid 6 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 168 document no.: pmc-2001304, issue 7 register 0x2069h:rxxg exact match vid 7 bit type function default bit 15 r unused bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r/w vid_match7[11] 0 bit 10 r/w vid_match7[10] 0 bit 9 r/w vid_match7[9] 0 bit 8 r/w vid_match7[8] 0 bit 7 r/w vid_match7[7] 0 bit 6 r/w vid_match7[6] 0 bit 5 r/w vid_match7[5] 0 bit 4 r/w vid_match7[4] 0 bit 3 r/w vid_match7[3] 0 bit 2 r/w vid_match7[2] 0 bit 1 r/w vid_match7[1] 0 bit 0 r/w vid_match7[0] 0 vid_match7[11:0] the exact match vid 7 register is used by th e address filter logic to compare on the 12 bit vid field on vlan tagged frames. this register is one of eight separate exact match vid registers that the address filter logic can use to compare on. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 169 document no.: pmc-2001304, issue 7 register 0x206ah: rxxg multicast hash low word bit type function default bit 15 r/w mhash[15] 0 bit 14 r/w mhash[14] 0 bit 13 r/w mhash[13] 0 bit 12 r/w mhash[12] 0 bit 11 r/w mhash[11] 0 bit 10 r/w mhash[10] 0 bit 9 r/w mhash[9] 0 bit 8 r/w mhash[8] 0 bit 7 r/w mhash[7] 0 bit 6 r/w mhash[6] 0 bit 5 r/w mhash[5] 0 bit 4 r/w mhash[4] 0 bit 3 r/w mhash[3] 0 bit 2 r/w mhash[2] 0 bit 1 r/w mhash[1] 0 bit 0 r/w mhash[0] 0 mhash[15:0] the mhash[15:0] is the low word of the 64-bi t multicast hash bin. this is used by the address filter logic for filtering of multicast addressed frames when mhash_en is ?1? in address filter control 2 register. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 170 document no.: pmc-2001304, issue 7 register 0x206bh:rxxg multicast hash midlow word bit type function default bit 15 r/w mhash[31] 0 bit 14 r/w mhash[30] 0 bit 13 r/w mhash[29] 0 bit 12 r/w mhash[28] 0 bit 11 r/w mhash[27] 0 bit 10 r/w mhash[26] 0 bit 9 r/w mhash[25] 0 bit 8 r/w mhash[24] 0 bit 7 r/w mhash[23] 0 bit 6 r/w mhash[22] 0 bit 5 r/w mhash[21] 0 bit 4 r/w mhash[20] 0 bit 3 r/w mhash[19] 0 bit 2 r/w mhash[18] 0 bit 1 r/w mhash[17] 0 bit 0 r/w mhash[16] 0 mhash[31:16] the mhash[31:16] is the midlow word of the 64-bit multicast hash bin. this is used by the address filter logic for filtering of multi cast addressed frames when mhash_en is ?1? in address filter control 2 register. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 171 document no.: pmc-2001304, issue 7 register 0x206ch:rxxg multicast hash midhigh word bit type function default bit 15 r/w mhash[47] 0 bit 14 r/w mhash[46] 0 bit 13 r/w mhash[45] 0 bit 12 r/w mhash[44] 0 bit 11 r/w mhash[43] 0 bit 10 r/w mhash[42] 0 bit 9 r/w mhash[41] 0 bit 8 r/w mhash[40] 0 bit 7 r/w mhash[39] 0 bit 6 r/w mhash[38] 0 bit 5 r/w mhash[37] 0 bit 4 r/w mhash[36] 0 bit 3 r/w mhash[35] 0 bit 2 r/w mhash[34] 0 bit 1 r/w mhash[33] 0 bit 0 r/w mhash[32] 0 mhash[47:32] the mhash[47:32] is the midhigh word of the 64-bit multicast hash bin. this is used by the address filter logic for filtering of multi cast addressed frames when mhash_en is ?1? in address filter control 2 register. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 172 document no.: pmc-2001304, issue 7 register 0x206dh:rxxg multicast hash high word bit type function default bit 15 r/w mhash[63] 0 bit 14 r/w mhash[62] 0 bit 13 r/w mhash[61] 0 bit 12 r/w mhash[60] 0 bit 11 r/w mhash[59] 0 bit 10 r/w mhash[58] 0 bit 9 r/w mhash[57] 0 bit 8 r/w mhash[56] 0 bit 7 r/w mhash[55] 0 bit 6 r/w mhash[54] 0 bit 5 r/w mhash[53] 0 bit 4 r/w mhash[52] 0 bit 3 r/w mhash[51] 0 bit 2 r/w mhash[50] 0 bit 1 r/w mhash[49] 0 bit 0 r/w mhash[48] 0 mhash[63:48] the mhash[63:48] is the high word of the 64-bi t multicast hash bin. this is used by the address filter logic for filtering of multicast addressed frames when mhash_en is ?1? in address filter control 2 register. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 173 document no.: pmc-2001304, issue 7 register 0x206eh:rxxg address filter control 0 bit type function default bit 15 r/w adrfilt_ctrl3[3] 0 bit 14 r/w adrfilt_ctrl3[2] 0 bit 13 r/w adrfilt_ctrl3[1] 0 bit 12 r/w adrfilt_ctrl3[0] 0 bit 11 r/w adrfilt_ctrl2[3] 0 bit 10 r/w adrfilt_ctrl2[2] 0 bit 9 r/w adrfilt_ctrl2[1] 0 bit 8 r/w adrfilt_ctrl2[1] 0 bit 7 r/w adrfilt_ctrl1[3] 0 bit 6 r/w adrfilt_ctrl1[2] 0 bit 5 r/w adrfilt_ctrl1[1] 0 bit 4 r/w adrfilt_ctrl1[0] 0 bit 3 r/w adrfilt_ctrl0[3] 0 bit 2 r/w adrfilt_ctrl0[2] 0 bit 1 r/w adrfilt_ctrl0[1] 0 bit 0 r/w adrfilt_ctrl0[0] 0 the address filter control 0 register contains the control bits for the first 4 filters 0-3, each filter needs 4 bits of control information. adrfilt_ctrl [3] forward enable bit. when this bit is ?1?, the address filter logic will only accept frames that match the corresponding exact match address register, and if the vlan enable bit is set the corresponding vid_match register. all ot her frames are filtered. when this bit is ?0?, the address filter logic will only discard frames that match the corresponding exact match address register, and if the vlan enab le bit is set the corresponding vid_match register. all other frames are filtered. adrfilt_ctrl[2] vlan enable bit. when this bit is ?1?, th e address filter logic will use the corresponding 12-bit vid_match register along with the corresponding exact match address register to perform the compare. when this bit is ?0 ?, the address filter logic will only use the corresponding exact match address register to perform the compare.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 174 document no.: pmc-2001304, issue 7 adrfilt_ctrl[1] source address enable bit. when this bit is ?0?, the address filter logic will use the destination address to perform a compare to the corresponding exact match address register. when this bit is ?1?, the addr ess filter logic will use the source address to perform a compare to the corresponding exact match address register. adrfilt_ctrl[0] match enable bit. when this bit is ?0 ?, the address filter logic will not use the corresponding filter. when this bit is ?1?, the address filter logic will use the corresponding filter based on adrfilt_ctrl?[3:1]. this bit must be written to ?0? before making any updates to the corresponding exact match address and vid registers., and can then be written as ?1? again. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 175 document no.: pmc-2001304, issue 7 register 0x206fh:rxxg address filter control 1 bit type function default bit 15 r/w adrfilt_ctrl7[3] 0 bit 14 r/w adrfilt_ctrl7[2] 0 bit 13 r/w adrfilt_ctrl7[1] 0 bit 12 r/w adrfilt_ctrl7[0] 0 bit 11 r/w adrfilt_ctrl6[3] 0 bit 10 r/w adrfilt_ctrl6[2] 0 bit 9 r/w adrfilt_ctrl6[1] 0 bit 8 r/w adrfilt_ctrl6[1] 0 bit 7 r/w adrfilt_ctrl5[3] 0 bit 6 r/w adrfilt_ctrl5[2] 0 bit 5 r/w adrfilt_ctrl5[1] 0 bit 4 r/w adrfilt_ctrl5[0] 0 bit 3 r/w adrfilt_ctrl4[3] 0 bit 2 r/w adrfilt_ctrl4[2] 0 bit 1 r/w adrfilt_ctrl4[1] 0 bit 0 r/w adrfilt_ctrl4[0] 0 the address filter control 1 register contains th e control bits for the second 4 filters 4-7, each filter needs 4 bits of control information. adrfilt_ctrl[3] forward enable bit. when this bit is ?1?, the address filter logic will only accept frames that match the corresponding exact match address register, and if the vlan enable bit is set the corresponding vid_match register. all ot her frames are filtered. when this bit is ?0?, the address filter logic will only discard frames that match the corresponding exact match address register, and if the vlan enab le bit is set the corresponding vid_match register. all other frames are filtered. adrfilt_ctrl[2] vlan enable bit. when this bit is ?1?, th e address filter logic will use the corresponding 12-bit vid_match register along with the corresponding exact match address register to perform the compare. when this bit is ?1 ?, the address filter logic will only use the corresponding exact match address register to perform the compare.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 176 document no.: pmc-2001304, issue 7 adrfilt_ctrl[1] source address enable bit. when this bit is ?0?, the address filter logic will use the destination address to perform a compare to the corresponding exact match address register. when this bit is ?1?, the addr ess filter logic will use the source address to perform a compare to the corresponding exact match address register. adrfilt_ctrl[0] match enable bit. when this bit is ?0 ?, the address filter logic will not use the corresponding filter. when this bit is ?1?, the address filter logic will use the corresponding filter based on adrfilt_ctrl?[3:1]. this bit must be written to ?0? before making any updates to the corresponding exact match address and vid registers., and can then be written as ?1? again. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 177 document no.: pmc-2001304, issue 7 register 0x2070h:rxxg address filter control 2 bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r unused x:high bit 4 r unused x:high bit 3 r unused x:high bit 2 r unused x:high bit 1 r/w pmode 1 bit 0 r/w mhash_en 0 mhash_en multicast hash filter enable. when this bit is ?1?, the 64-bit multicast hash filter function will look at all multicast -addressed frames for f ilter processing. when this bit is ?0?, no multicast hash look-ups are performed. pmode promiscuous mode. when this bit is ?1?, th e pm3392 will allow all frames to pass through to the pl4 interface regardless of the da /sa addresses, unless address filtering logic is enabled and there is a match to filter the incoming frame based on the da/sa/vid fields. when this bit is ?0?, the pm3392 will not a llow any frames to pass through to the pl4 interface unless address filtering logic is enabled and there is a match to the incoming frame. note: please refer to 13.17 for the proper use of these registers.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 178 document no.: pmc-2001304, issue 7 register 0x2080h:r64b66b configuration bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r/w tip 0 bit 12 r reserved 0 bit 11 r/w jitter_pattern_slct 0 bit 10 r/w jitter_test_enable 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r unused 0 bit 6 r unused 0 bit 5 r unused 0 bit 4 r reserved 0 bit 3 r unused 1 bit 2 r unused 0 bit 1 r/w int_en 0 bit 0 r reserved 1 int_en when ?1?, the interrupts are enabled. when ?0?, the interrupts are disabled. jitter_test_enable setting this bit to ?1? enables jitter test mode . this disables the ber and receive state machines. jitter_pattern_slct setting this to ?1? causes the r64b66b to look for the all zeroes pattern (128 zeroes). setting it to ?0? causes it to look for one of the three local fault patterns, types 0x2d, 0x4b, and 0x55. type 0x66 is left out because it codes for start of frame. tip writing a ?1? to this bit copies the current value of registers 0x3 ? 0x7 to a set of shadow registers. when this bit is read as ?1? the tran sfer is still in progress, the transfer typically takes a few sys_clkx2 cycles. when this bit is read as ?0?, the transfer is complete. during the transfer the busy tsb output is also ?1?.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 179 document no.: pmc-2001304, issue 7 register 0x2081h:r64b66b interrupt mask bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r/w link_faile 0 bit 4 r/w rx_lfe 0 bit 3 r/w rx_rfe 0 bit 2 r/w lose 0 bit 1 r/w hi_bere 0 bit 0 r/w sync_erre 0 sync_erre: sync error mask bit when ?0?, masks the interrupt status that the sync_err pin asserted due to a loss of signal from the optics. when ?1?, will cause the interrupt pin to assert when the sync_err pin asserted due to a loss of signal from the optics. hi_bere: high bit-error-rate mask bit when ?0?, masks the interrupt status indicating a high bit-error-rate state. when ?1?, will cause the interrupt pin to assert during a high bit-error-rate state. lose: loss of sync mask bit when ?0?, masks the interrupt status indicating an out of sync state. when ?1?, will cause the interrupt pin to assert for an out of sync state. rx_rfe: receive remote fault mask bit when ?0?, masks the interrupt status that th e r64b66b block has just received at least 3 remote fault messages.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 180 document no.: pmc-2001304, issue 7 when ?1?, will cause the interrupt pin to assert when the r64b66b block has receives at least 3 remote fault messages. rx_lfe: receive local fault mask bit when ?0?, masks the interrupt status that th e r64b66b block has just received at least 3 local fault messages. when ?1?, will cause the interrupt pin to assert when the r64b66b block has receives at least 3 local fault messages. link_faile: link failed mask bit when ?0?, masks the interrupt status that the r64b66b link has failed due to a high bit error rate or a loss of sync. when ?1?, will cause the interrupt pin to asser t when the r64b66b link fails due to a high bit error rate or a loss of sync.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 181 document no.: pmc-2001304, issue 7 register 0x2082h:r64b66b interrupt status bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r link_faili 0 bit 4 r rx_lfi 0 bit 3 r rx_rfi 0 bit 2 r losi 0 bit 1 r hi_beri 0 bit 0 r sync_erri 0 sync_erri: sync error status bit when ?1?, signals status that the sync_e rr pin asserted due to a loss of signal from the optics. when ?0?, the sync_err pin is low. note: this bit is a latching high bit and will assert on a rising edge event. this bit will clear on a read from this register hi_beri: high bit-error-rate status bit when ?1?, signals a hi bit-error-rate state. when ?0?, the ber is below 16 errors per 125us. note: this bit is a latching high bit and will assert on a rising edge event. this bit will clear on a read from this register losi: loss of sync interrupt status bit when ?1?, signals an out of sync state. sync can be lost with reset, sync_err input, or more than 32 invalid sync fields in 64 66-bit frames.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 182 document no.: pmc-2001304, issue 7 when ?0?, the sync detector logic is sync?d. note: this bit is a latching high bit and will assert on a rising edge event. this bit will clear on a read from this register rx_rfi: receive remote fault interrupt status bit when ?1?, signals status that the r64b66b bl ock has just received at least 3 remote fault messages. when ?0?, means that the pcs is not in a remote fault state. note: this bit is a latching high bit and will assert on a rising edge event. this bit will clear on a read from this register rx_lfi: receive local fault interrupt status bit when ?1?, signal status that the r64b66b bl ock has just received at least 3 local fault messages. when ?0?, means that the pcs is not in a local fault state. note: this bit is a latching high bit and will assert on a rising edge event. this bit will clear on a read from this register link_fail: link failed interrupt status bit when ?1?, signals status that the r64b66b li nk has failed due to either loss of sync or a local fault status was observed. when ?0?, means that the receive state machine is receiving good data. note: this bit is a latching high bit and will assert on a rising edge event. this bit will clear on a read from this register
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 183 document no.: pmc-2001304, issue 7 register 0x2083h:r64b66b status bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r link_fail 1 bit 4 r rx_lf 0 bit 3 r rx_rf 0 bit 2 r los 1 bit 1 r hi_ber 0 bit 0 r sync_err x:high note: to update these status bits one must first write to the r64b66b tip bit (bit-15) in register 0x2080 r64b66b configuration. then a read can be performed to get the status. sync_err: sync error current status bit when ?1?, signals status that the sync_e rr pin asserted due to a loss of signal from the optics. when ?0?, the sync_err pin is low. hi_ber: high bit-error-rate current status bit when ?1?, signals a hi bit-error-rate state. when ?0?, the ber is below 16 errors per 125us. los: loss of sync current status bit when ?1?, signals an out of sync state. sync can be lost with reset, sync_err input, or more than 32 invalid sync fields in 64 66-bit frames. when ?0?, the sync detector logic is sync?d.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 184 document no.: pmc-2001304, issue 7 rx_rf: receive remote fault current status bit when ?1?, signals status that the r64b66b bl ock has just received at least 3 remote fault messages. when ?0?, means that the pcs is not in a remote fault state. rx_lf: receive local fault current status bit when ?1?, signal status that the r64b66b bl ock has just received at least 3 local fault messages. when ?0?, means that the pcs is not in a local fault state. link_fail: link failed current status bit when ?1?, signals status that the r64b66b link has failed due to the either loss of sync or a local fault status was observed. when ?0?, means that the r64b66b link is up.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 185 document no.: pmc-2001304, issue 7 register 0x2084h:r64b66b error_frame_cnt bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r error_frame_cnt[7] x:high bit 6 r error_frame_cnt[6] x:high bit 5 r error_frame_cnt[5] x:high bit 4 r error_frame_cnt[4] x:high bit 3 r error_frame_cnt[3] x:high bit 2 r error_frame_cnt[2] x:high bit 1 r error_frame_cnt[1] x:high bit 0 r error_frame_cnt[0] x:high error_frame_cnt[7:0] these bits indicate the number of invalid pcs code sequences detected in the ingress path. the counter only increments when the r64b66b block is in a sync?d state. the counter should be polled regularly to avoid saturating. the counter can saturate at values 0x00fe or 0x00ff. this register is cleared on read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 186 document no.: pmc-2001304, issue 7 register 0x2085h:r64b66b frame_lock_count[15:0] bit type function default bit 15 r frame_lock _count[15] x:high bit 14 r frame_lock _count[14] x:high bit 13 r frame_lock _count[13] x:high bit 12 r frame_lock _count[12] x:high bit 11 r frame_lock _count[11] x:high bit 10 r frame_lock _count[10] x:high bit 9 r frame_lock_count[9] x:high bit 8 r frame_lock_count[8] x:high bit 7 r frame_lock_count[7] x:high bit 6 r frame_lock_count[6] x:high bit 5 r frame_lock_count[5] x:high bit 4 r frame_lock_count[4] x:high bit 3 r frame_lock_count[3] x:high bit 2 r frame_lock_count[2] x:high bit 1 r frame_lock_count[1] x:high bit 0 r frame_lock_count[0] x:high frame_lock_count[15:0] these bits indicate the number times the synchronizer state machine has gone from a non- sync?d state to a sync?d state. the counter should be polled regularly to avoid saturating. the counter can saturate at values 0x ffff or 0xfffe. this register is cleared on read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 187 document no.: pmc-2001304, issue 7 register 0x2086h:r64b66b hi_ber_cnt[4:0] bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r unused x:high bit 6 r unused x:high bit 5 r hi_ber_cnt[5] x:high bit 4 r hi_ber_cnt[4] x:high bit 3 r hi_ber_cnt[3] x:high bit 2 r hi_ber_cnt[2] x:high bit 1 r hi_ber_cnt[1] x:high bit 0 r hi_ber_cnt[0] x:high hi_ber_cnt[5:0] these bits indicate the number of bit errors during a 125us interval. the counter resets to zero after every 125us. the counter only incr ements when the r64b66b block is in a sync?d state. this register is cleared on read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 188 document no.: pmc-2001304, issue 7 register 0x2087h: r64b66b jitter_cnt[15:0] bit type function default bit 15 r jitter_cnt[15] x bit 14 r jitter_cnt[14] x bit 13 r jitter_cnt[13] x bit 12 r jitter_cnt[12] x bit 11 r jitter_cnt[11] x bit 10 r jitter_cnt[10] x bit 9 r jitter_cnt[9] x bit 8 r jitter_cnt[8] x bit 7 r jitter_cnt[7] x bit 6 r jitter_cnt[6] x bit 5 r jitter_cnt[5] x bit 4 r jitter_cnt[4] x bit 3 r jitter_cnt[3] x bit 2 r jitter_cnt[2] x bit 1 r jitter_cnt[1] x bit 0 r jitter_cnt[0] x this register is updated by setting the tip bit (bit-13) in register 0x2080 r64b668 configuration. jitter_cnt[15:0] putting the r64b66b into jitter mode (register 0, bit 10) enables this counter. this counter is incremented for every unscrambled 66 bit frame that doesn?t match the expected frame data. the expected frame type is set by register 0, bit 11. register 7h is cleared upon read. see section 49.2.12 of the ieee 802.3ae sta ndard for a description of the receive jitter algorithm. the counter can saturate at values 0x ffff or 0xfffe.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 189 document no.: pmc-2001304, issue 7 register 0x2100h:mstat control bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r/w write 0 bit 1 r/w clear 0 bit 0 r/w snap 0 the mstat control register provides general control over the mstat. snap the snap bit is used to snap all management statistics counters into their complimentary system probe shadow registers for full static system probes. the snap bit will perform the copy operation when set high (logic 1). the snap bit will automatically clear itself (logic 0) after two positive clock edges (the clock can be rdcki or tdcki). clear the clear bit is used to clear all management statistic registers. the clear bit clear all registers when set high (logic 1). the clear bit will automatically clear itself (logic 0) after two positive clock edges (the clock can be rdcki or tdcki). write the write bit is used to initiate a data update write to the selected counter indicated by the mstat counter write address register. the contents of the mstat counter write data registers will be copied into the associa tive counter. the write is initiated by setting this bit high (logic 1). the write bit will automatically clear itself (logic 0) after two positive clock edges (the clock can be rdcki or tdcki).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 190 document no.: pmc-2001304, issue 7 register 0x2101h:mstat counter rollover 0 bit type function default bit 15 r framestoolongerrors 0 bit 14 r reserved 0 bit 13 r inrangelengtherrors 0 bit 12 r symbolerror 0 bit 11 r frameslostduetointernalmacerror 0 bit 10 r framechecksequenceerrors 0 bit 9 r maccontrolframereceived 0 bit 8 r pausemaccontrolframereceived 0 bit 7 r taggedframesreceived 0 bit 6 r broadcastframesreceivedok 0 bit 5 r multicastframesreceivedok 0 bit 4 r unicastframesreceivedok 0 bit 3 r octetsreceived 0 bit 2 r framesreceived 0 bit 1 r octetsreceivedok 0 bit 0 r framesreceivedok 0 the mstat counter rollover registers provide sticky indication of counter roll over conditions. reading this register clears all bits within this register. each bit represents the given counter name as documented.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 191 document no.: pmc-2001304, issue 7 register 0x2102h:mstat counter rollover 1 bit type function default bit 15 r reserved 0 bit 14 r filteredbroadcastframes 0 bit 13 r filteredmulticastframes 0 bit 12 r filteredunicastframes 0 bit 11 r filteredoctets 0 bit 10 r jumbooctetsreceivedok 0 bit 9 r receiveframes1519tomaxoctets 0 bit 8 r receiveframes1024to1518octets 0 bit 7 r receiveframes512to1023octets 0 bit 6 r receiveframes256to511octets 0 bit 5 r receiveframes128to255octets 0 bit 4 r receiveframes65to127octets 0 bit 3 r receiveframes64octets 0 bit 2 r undersizedframes 0 bit 1 r fragments 0 bit 0 r jabbers 0 the mstat counter rollover registers provide sticky indication of counter roll over conditions. reading this register clears all bits within this register. each bit represents the given counter name as documented.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 192 document no.: pmc-2001304, issue 7 register 0x2103h:mstat counter rollover 2 bit type function default bit 15 r transmittedframes128to255octets 0 bit 14 r transmittedframes65to127octets 0 bit 13 r transmittedframes64octets 0 bit 12 r macctrlframestransmitted 0 bit 11 r pausemacctrlframestransmitted 0 bit 10 r broadcastframestransmittedok 0 bit 9 r broadcastframestranmittedattempted 0 bit 8 r multicastframestransmittedok 0 bit 7 r multicastframestransmittedattempted 0 bit 6 r unicastframestransmittedok 0 bit 5 r unicastframestransmittedattempted 0 bit 4 r transmitsystemerror 0 bit 3 r frameslostduetointernalmactransmissionerror 0 bit 2 r octetstransmitted 0 bit 1 r octetstransmittedok 0 bit 0 r framestransmitteok 0 the mstat counter rollover registers provide sticky indication of counter roll over conditions. reading this register clears all bits within this register. each bit represents the given counter name as documented.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 193 document no.: pmc-2001304, issue 7 register 0x2104h:mstat counter rollover 3 bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r jumbooctetstransmittedok 0 bit 3 r transmittedframes1519tomaxoctets 0 bit 2 r transmittedframes1024to1518octets 0 bit 1 r transmittedframes512to1023octets 0 bit 0 r transmittedframes256to511octets 0 the mstat counter rollover registers provide sticky indication of counter roll over conditions. reading this register clears all bits within this register. each bit represents the given counter name as documented.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 194 document no.: pmc-2001304, issue 7 register 0x2105h:mstat interrupt mask 0 bit type function default bit 15 r/w mask0[15] 0 bit 14 r/w mask0[14] 0 bit 13 r/w mask0[13] 0 bit 12 r/w mask0[12] 0 bit 11 r/w mask0[11] 0 bit 10 r/w mask0[10] 0 bit 9 r/w mask0[9] 0 bit 8 r/w mask0[8] 0 bit 7 r/w mask0[7] 0 bit 6 r/w mask0[6] 0 bit 5 r/w mask0[5] 0 bit 4 r/w mask0[4] 0 bit 3 r/w mask0[3] 0 bit 2 r/w mask0[2] 0 bit 1 r/w mask0[1] 0 bit 0 r/w mask0[0] 0 the mstat interrupt mask registers provide programmable interrupt masking of the mstat counter rollover register bits. mask0[15:0] the mask0[15:0] bits are used as a logical mask for each corresponding bit in the mstat counter rollover register 0 . if the mask bit is high (logic 1), the given counter overflow condition in the mstat counter rollover register 0 will cause the mstat to assert the int pin high (logic 1). if the ma sk bit is low (logic 0), the corresponding mstat counter rollover register 0 bit state has no effect on the mstat int pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 195 document no.: pmc-2001304, issue 7 register 0x2106h:mstat interrupt mask 1 bit type function default bit 15 r reserved 0 bit 14 r/w mask1[14] 0 bit 13 r/w mask1[13] 0 bit 12 r/w mask1[12] 0 bit 11 r/w mask1[11] 0 bit 10 r/w mask1[10] 0 bit 9 r/w mask1[9] 0 bit 8 r/w mask1[8] 0 bit 7 r/w mask1[7] 0 bit 6 r/w mask1[6] 0 bit 5 r/w mask1[5] 0 bit 4 r/w mask1[4] 0 bit 3 r/w mask1[3] 0 bit 2 r/w mask1[2] 0 bit 1 r/w mask1[1] 0 bit 0 r/w mask1[0] 0 the mstat interrupt mask registers provide programmable interrupt masking of the mstat counter rollover register bits. mask1[14:0] the mask1[14:0] bits are used as a logical mask for each corresponding bit in the mstat counter rollover register 1 . if the mask bit is high (logic 1), the given counter overflow condition in the mstat counter rollover register 1 will cause the mstat to assert the int pin high (logic 1). if the ma sk bit is low (logic 0), the corresponding mstat counter rollover register 1 bit state has no effect on the mstat int pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 196 document no.: pmc-2001304, issue 7 register 0x2107h:mstat interrupt mask 2 bit type function default bit 15 r/w mask2[15] 0 bit 14 r/w mask2[14] 0 bit 13 r/w mask2[13] 0 bit 12 r/w mask2[12] 0 bit 11 r/w mask2[11] 0 bit 10 r/w mask2[10] 0 bit 9 r/w mask2[9] 0 bit 8 r/w mask2[8] 0 bit 7 r/w mask2[7] 0 bit 6 r/w mask2[6] 0 bit 5 r/w mask2[5] 0 bit 4 r/w mask2[4] 0 bit 3 r/w mask2[3] 0 bit 2 r/w mask2[2] 0 bit 1 r/w mask2[1] 0 bit 0 r/w mask2[0] 0 the mstat interrupt mask registers provide programmable interrupt masking of the mstat counter rollover register bits. mask2[15:0] the mask2[15:0] bits are used as a logical mask for each corresponding bit in the mstat counter rollover register 2 . if the mask bit is high (logic 1), the given counter overflow condition in the mstat counter rollover register 2 will cause the mstat to assert the int pin high (logic 1). if the ma sk bit is low (logic 0), the corresponding mstat counter rollover register 2 bit state has no effect on the mstat int pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 197 document no.: pmc-2001304, issue 7 register 0x2108h:mstat interrupt mask 3 bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r/w mask3[5] 0 bit 4 r/w mask3[4] 0 bit 3 r/w mask3[3] 0 bit 2 r/w mask3[2] 0 bit 1 r/w mask3[1] 0 bit 0 r/w mask3[0] 0 the mstat interrupt mask registers provide programmable interrupt masking of the mstat counter rollover register bits. mask3[5:0] the mask3[5:0] bits are used as a logica l mask for each corresponding bit in the mstat counter rollover register 3 . if the mask bit is high (logic 1), the given counter overflow condition in the mstat counter rollover register 3 will cause the mstat to assert the int pin high (logic 1). if the ma sk bit is low (logic 0), the corresponding mstat counter rollover register 3 bit state has no effect on the mstat int pin.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 198 document no.: pmc-2001304, issue 7 register 0x2109h:mstat counter write address bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r/w address[5] 0 bit 4 r/w address[4] 0 bit 3 r/w address[3] 0 bit 2 r/w address[2] 0 bit 1 r/w address[1] 0 bit 0 r/w address[0] 0 the mstat counter write address register provides the write address used during a write operation to the mstat counters. address[5:0] the address[5:0] bits are used as the write address during a write operation to the mstat counters. a proper counter address mu st be written to the mstat counter write address prior to initiating a write operation via the write bit in the mstat control register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 199 document no.: pmc-2001304, issue 7 register 0x210ah:mstat counter write data low bit type function default bit 15 r/w data[15] 0 bit 14 r/w data[14] 0 bit 13 r/w data[13] 0 bit 12 r/w data[12] 0 bit 11 r/w data[11] 0 bit 10 r/w data[10] 0 bit 9 r/w data[9] 0 bit 8 r/w data[8] 0 bit 7 r/w data[7] 0 bit 6 r/w data[6] 0 bit 5 r/w data[5] 0 bit 4 r/w data[4] 0 bit 3 r/w data[3] 0 bit 2 r/w data[2] 0 bit 1 r/w data[1] 0 bit 0 r/w data[0] 0 the mstat counter write data registers provide the write data used during a write operation to the mstat counters. the mstat counter write data registers are partitioned into low, middle, and high register entities. data[15:0] the data[15:0] bits are used as the write data during a write operation to the mstat counters. the proper counter data must be written to the mstat counter write data registers prior to initiating a write operation via the write bit in the mstat control register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 200 document no.: pmc-2001304, issue 7 register 0x210bh:mstat counter write data middle bit type function default bit 15 r/w data[31] 0 bit 14 r/w data[30] 0 bit 13 r/w data[29] 0 bit 12 r/w data[28] 0 bit 11 r/w data[27] 0 bit 10 r/w data[26] 0 bit 9 r/w data[25] 0 bit 8 r/w data[24] 0 bit 7 r/w data[23] 0 bit 6 r/w data[22] 0 bit 5 r/w data[21] 0 bit 4 r/w data[20] 0 bit 3 r/w data[19] 0 bit 2 r/w data[18] 0 bit 1 r/w data[17] 0 bit 0 r/w data[16] 0 the mstat counter write data registers provide the write data used during a write operation to the mstat counters. the mstat counter write data registers are partitioned into low, middle, and high register entities. data[31:16] the data[31:16] bits are used as the write data during a write operation to the mstat counters. the proper counter data must be written to the mstat counter write data registers prior to initiating a write operation via the write bit in the mstat control register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 201 document no.: pmc-2001304, issue 7 register 0x210ch:mstat counter write data high bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r/w data[39] 0 bit 6 r/w data[38] 0 bit 5 r/w data[37] 0 bit 4 r/w data[36] 0 bit 3 r/w data[35] 0 bit 2 r/w data[34] 0 bit 1 r/w data[33] 0 bit 0 r/w data[32] 0 the mstat counter write data registers provide the write data used during a write operation to the mstat counters. the mstat counter write data registers are partitioned into low, middle, and high register entities. data[39:32] the data[39:32] bits are used as the write data during a write operation to the mstat counters. the proper counter data must be written to the mstat counter write data registers prior to initiating a write operation via the write bit in the mstat control register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 202 document no.: pmc-2001304, issue 7 register 0x2110h to 0x21e6h:mstat receive statistical counters? low bit type function default bit 15 r count[15] 0 bit 14 r count[14] 0 bit 13 r count[13] 0 bit 12 r count[12] 0 bit 11 r count[11] 0 bit 10 r count[10] 0 bit 9 r count[9] 0 bit 8 r count[8] 0 bit 7 r count[7] 0 bit 6 r count[6] 0 bit 5 r count[5] 0 bit 4 r count[4] 0 bit 3 r count[3] 0 bit 2 r count[2] 0 bit 1 r count[1] 0 bit 0 r count[0] 0 the mstat statistical counters are defined in table 15. the mstat statistical counter is a 40-bits counter. the mstat statistical counter s represent the individual counters split between high, middle, and low registers. the low register contains bits 15:0, the middle register contains bits 31:16, and the high register contains bits 39:32 as well as 8 unused or reserved bits in the msb of the high register. count[15:0] the count[15:0] bits are used as the low 16-bit of the counter.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 203 document no.: pmc-2001304, issue 7 register 0x2110h to 0x21e6h:mstat receive statistical counters? middle bit type function default bit 15 r count[31] 0 bit 14 r count[30] 0 bit 13 r count[29] 0 bit 12 r count[28] 0 bit 11 r count[27] 0 bit 10 r count[26] 0 bit 9 r count[25] 0 bit 8 r count[24] 0 bit 7 r count[23] 0 bit 6 r count[22] 0 bit 5 r count[21] 0 bit 4 r count[20] 0 bit 3 r count[19] 0 bit 2 r count[18] 0 bit 1 r count[17] 0 bit 0 r count[16] 0 the mstat statistical counters are defined in table 15. the mstat statistical counter is a 40-bits counter. the mstat statistical counter s represent the individual counters split between high, middle, and low registers. the low register contains bits 15:0, the middle register contains bits 31:16, and the high register contains bits 39:32 as well as 8 unused or reserved bits in the msb of the high register. count[31:16] the count[31:16] bits are used as the middle 16-bit of the counter.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 204 document no.: pmc-2001304, issue 7 register 0x2110h to 0x21e6h:mstat receive statistical counters? high bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r/w count[39] 0 bit 6 r/w count[38] 0 bit 5 r/w count[37] 0 bit 4 r/w count[36] 0 bit 3 r/w count[35] 0 bit 2 r/w count[34] 0 bit 1 r/w count[33] 0 bit 0 r/w count[32] 0 the mstat statistical counters are defined in table 15. the mstat statistical counter is a 40-bits counter. the mstat statistical counter s represent the individual counters split between high, middle, and low registers. the low register contains bits 15:0, the middle register contains bits 31:16, and the high register contains bits 39:32 as well as 8 unused or reserved bits in the msb of the high register. count[39:32] the count[39:32] bits are used as the high 8-bit of the counter.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 205 document no.: pmc-2001304, issue 7 table 15 mstat counter description mstat counter registers read address 0x2110 low 0x2111 mid 0x2112 high framesreceivedok contains a count of frames that are successfully received. this does not include frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, or undersizedframes. mstat counter write address = 0x0 0x2114 low 0x2115 mid 0x2116 high octetsreceivedok contains a count of data and padding octets in frames (not including preamble, sfd, destination/source a ddress, type/length field, q-tag prefix or fcs) that are successfully received. this does not include octets in frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, undersizedframes ifinoctets (mib-ii) can be computed using the following: ifinoctets = octetsreceivedok + (18 * framesreceivedok) ifinoctets includes the count of data, padding, destination/source address, length/type field, q-ta g prefix, and fcs. (excludes preamble and sfd). mstat counter write address = 0x1 0x2118 low 0x2119 mid 0x211a high framesreceived the total number of frames (including bad frames, unicast frames, broadcast frames, and multicast frames) received. this count includes those frames of jumbo size. mstat counter write address = 0x2 0x211c low 0x211d mid 0x211e high octetsreceived the total number of octets of data (including those in bad frames) received (excluding framing bits but including fcs octets). this includes the count of bytes from the first byte of the destination address to the last byte of the fcs field. mstat counter write address = 0x3
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 206 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x2120 low 0x2121 mid 0x2122 high unicastframesreceivedok contains a count of frames that are successfully received and are directed to a unicast group address. this does not include octets in frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, or undersizedframes. mstat counter write address = 0x4 0x2124 low 0x2125 mid 0x2126 high multicastframesreceivedok contains count of frames that are successfully received and are directed to a multicast group address. this counter will not increment for frames classified as unicast or broadcast. this does not include frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, or undersizedframes. mstat counter write address = 0x5 0x2128 low 0x2129 mid 0x212a high broadcastframesreceivedok contains a count of frames that are successfully received and are directed to the broadcast group address. this counter will not increment for frames classified as unicast or multicast. this does not include frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, or undersizedframes. mstat counter write address = 0x6 0x212c low 0x212d mid 0x212e high taggedframesreceived contains a count of all tagged frames that are received. mstat counter write address = 0x7
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 207 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x2130 low 0x2131 mid 0x2132 high pausemaccontrolframereceived contains a count of mac control frames passed by the mac sublayer to the mac control sublayer. this counter is incremented when a receiveframe function call returns a valid frame with: a lengthortype field value equal to the reserved type for 802.3_mac_control as specified in 802.3-1998 (31.4.1.3), and an opcode indicating the pause operation. this does not include frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, or undersizedframes. mstat counter write address = 0x8 0x2134 low 0x2135 mid 0x2136 high maccontrolframereceived contains a count of mac control frames passed by the mac sublayer to the mac control sublayer. this counter is incremented when a receiveframe function call returns a valid frame with: (1) a lengthortype field value equal to the reserved type for 802.3_mac_control as specified in 802.3-1998 (31.4.1.3). this does not include frames received that are classified under: framechecksequenceerrors, frameslostduetointernalmacerror, symbolerror, inrangelengtherrors, outofrangelengtherrors, framestoolongerrors, jabbers, fragments, or undersizedframes. mstat counter write address = 0x9 0x2138 low 0x2139 mid 0x213a high framechecksequenceerrors contains a count of receive frames t hat are an integral number of octets in length and do not pass the fcs c heck. this does not include frames received that are too long(jabber s), or too short (fragments). mstat counter write address = 0xa 0x213c low 0x213d mid 0x213e high frameslostduetointernalmacerror contains a count of frames that would otherwise be received by the device, but could not be accepted due to an internal mac sublayer receive error (i.e. fifo overrun). if this counter is incremented, then none of the other error counters in this section are incremented. mstat counter write address = 0xb
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 208 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x2140 low 0x2141 mid 0x2142 high symbolerror a count of the number of times when valid length frame was received at the port and during which time there was at least one occurrence of an event that causes the phy to indica te ?data reception error? or invalid ?data symbol error.? this counter shall be incremented only once per valid carrierevent. this counter will increment when the receive pcs experiences the following errors: ? receive state machine transitions to the error state as per the 802.3ae standard ? loss of sync ? hi_ber state ? receptions of ordered sets mstat counter write address = 0xc 0x2144 low 0x2145 mid 0x2146 high inrangelengtherrors contains a count of frames with a length/type field value between 46 and 1500 that does not match the number of mac client data octets received. the counter also increments for frames whose length/type field value is from 0 to 45 regardless of the number of mac client data octets received. mstat counter write address = 0xd 0x214c low 0x214d mid 0x214e high framestoolongerrors contains a count of frames receiv ed that exceed the maximum permitted frame size and have no other errors. this counter is aware of both tagged and non tagged frames as well as frames of jumbo size. mstat counter write address = 0xf 0x2150 low 0x2151 mid 0x2152 high jabbers contains a count of the total number of frames received that were longer than the maximum permitted frame size and had a bad frame check sequence (fcs). mstat counter write address = 0x10
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 209 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x2154 low 0x2155 mid 0x2156 high fragments the total number of frames received that were less than minimum permitted frame size (64 octets long excluding framing bits, but including fcs octets) and had a bad frame check sequence (fcs). mstat counter write address = 0x11 0x2158 low 0x2159 mid 0x215a high undersizedframes the total number of frames received that were less than the minimum permitted frame size (64 octets long excluding framing bits, but including fcs octets) and were otherwise well formed. mstat counter write address = 0x12 0x215c low 0x215d mid 0x215e high receiveframes64octets the total number of frames (including bad frames) received that were 64 octets in length (excluding framing bits but including fcs octets). mstat counter write address = 0x13 0x2160 low 0x2161 mid 0x2162 high receiveframes65to127octets the total number of frames (including bad frames) received that were between 65 and 127 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x14 0x2164 low 0x2165 mid 0x2166 high receiveframes128to255octets the total number of frames (including bad frames) received that were between 128 and 255 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x15 0x2168 low 0x2169 mid 0x216a high receiveframes256to511octets the total number of frames (including bad frames) received that were between 256 and 511 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x16 0x216c low 0x216d mid 0x216e high receiveframes512to1023octets the total number of frames (including bad frames) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x17
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 210 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x2170 low 0x2171 mid 0x2172 high receiveframes1024to1518octets the total number of frames (including bad frames) received that were between 1024 and (1518 octets for untagged frames and 1522 octets for vlan tagged frames) in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x18 0x2174 low 0x2175 mid 0x2176 high receiveframes1519tomaxoctets the total number of frames (including bad frames) received that were between the maximum normal frame lengths (1518 octets for untagged frames and 1522 octets for tagged frames) and maximum jumbo frame lengths (i.e. 9600 octets) (excluding framing bits but including fcs octets). mstat counter write address = 0x19 0x2178 low 0x2179 mid 0x217a high jumbooctetsreceivedok the total number of octets (excluding bad frames) received that were between the maximum normal frame lengths (1518 octets for untagged frames and 1522 octets for tagged frames) and maximum jumbo frame lengths (i.e. up to maxframesize) (excluding framing bits but including fcs octets). mstat counter write address = 0x1a 0x217c low 0x217d mid 0x217e high filteredoctets the total number of octets that woul d normally be passed to the link that are dropped because of filtering rules. mstat counter write address = 0x1b 0x2180 low 0x2181 mid 0x2182 high filteredunicastframes the total number of unicast classified fames that would normally be passed to the link that are dro pped because of filtering rules. mstat counter write address = 0x1c 0x2184 low 0x2185 mid 0x2186 high filteredmulticastframes the total number of multicast frames that would normally be passed to the link that are dropped bec ause of filtering rules. mstat counter write address = 0x1d 0x2188 low 0x2189 mid 0x218a high filteredbroadcastframes the total number of broadcast frames that would normally be passed to the link that are dropped bec ause of filtering rules. mstat counter write address = 0x1e 0x2190 low framestransmittedok
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 211 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x2191 mid 0x2192 high contains the count of frames that are successfully transmitted over the mac interface. mstat counter write address = 0x20 0x2194 low 0x2195 mid 0x2196 high octetstransmittedok contains a count of data and paddi ng (excluding preamble, sfd, destination/source address, length/ty pe field, q-tag prefix, and fcs) octets of frames that are succe ssfully transmitted over the mac interface. ifoutoctets (mib-ii) can be computed using the following: ifoutoctets = octetstransmittedok + (18 * framestransmittedok) ifoutoctets includes the count of data, padding, destination/source address, lengt h/type field, q-tag prefix, and fcs. (excludes preamble and sfd). mstat counter write address = 0x21 0x2198 low 0x2199 mid 0x219a high octetstransmitted contains a count of data and paddi ng (excluding preamble, sfd, destination/source address, length/ty pe field, q-tag prefix, and fcs) octets of frames that are attemp ted to be transmitted over the mac interface. mstat counter write address = 0x22 0x219c low 0x219d mid 0x219e high frameslostduetointernalmactransmissionerror contains a count of frames that wo uld otherwise be transmitted by the device, but because of a mac fifo underrun could not be sent correctly. if this counter is incremented, then none of the other error counters in this section are incremented. mstat counter write address = 0x23 0x21a0 low 0x21a1 mid 0x21a2 high transmitsystemerror contains a count of frames that wo uld otherwise be transmitted by the device, but could not be sent due to an indication from the pos-phy level 4 error signal being asserted, an oversize frame being transmitted, or an internal crc erro r discovered that was generated from the upstream device. if this counter is incremented, then none of the other error counters in this section are incremented. mstat counter write address = 0x24 0x21a4 low 0x21a5 mid unicastframestransmittedattempted contains a count of frames that are requested to be transmitted to a group unicast destination address. this count includes those frames that
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 212 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x21a6 high were discarded or not sent. mstat counter write address = 0x25 0x21a8 low 0x21a9 mid 0x21aa high unicastframestransmittedok contains a count of frames that ar e successfully transmitted via the mac interface to a group unicast destination address. mstat counter write address = 0x26 0x21ac low 0x21ad mid 0x21ae high multicastframestransmittedattempted contains a count of frames that are requested to be transmitted to a group multicast destination address. this count includes those frames that were discarded or not sent. this count is not updated by broadcast frame transmission. mstat counter write address = 0x27 0x21b0 low 0x21b1 mid 0x21b2 high multicastframestransmittedok contains a count of frames that are successfully transmitted to a group multicast destination. this count is not updated by broadcast frame transmission. mstat counter write address = 0x28 0x21b4 low 0x21b5 mid 0x21b6 high broadcastframestransmittedattempted contains a count of the frames that were requested to be transmitted to a broadcast address. this count in cludes those frames that were discarded or not sent. this count is not updated by multicast frame transmission. mstat counter write address = 0x29 0x21b8 low 0x21b9 mid 0x21ba high broadcastframestransmittedok contains a count of the frames that were successfully transmitted to the broadcast address. this count is not updated by multicast frame transmission. mstat counter write address = 0x2a
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 213 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x21bc low 0x21bd mid 0x21be high pausemacctrlframestransmitted contains a count of pause frames pas sed to the mac control sublayer for transmission. this counter is incremented when a request to send the pause control frame is generated. the count only includes pause mac control frames that are generat ed by the transmit mac within the pm3392, i.e. iflx fifo almost full threshold is reached, the external pause pin is asserted or the hostpau se bit is asserted in the mac. this does not include any pause mac control frames coming across the pl4 interface. mstat counter write address = 0x2b 0x21c0 low 0x21c1 mid 0x21c2 high macctrlframestransmitted contains a count of frames passed to the mac sublayer for transmission. this counter is incremented when a control frame is transmitted out of the mac. this does not include any mac control frames coming across the pl4 interface. mstat counter write address = 0x2c 0x21c4 low 0x21c5 mid 0x21c6 high transmittedframes64octets the total number of frames (includi ng bad frames) transmitted that were 64 octets in length (excluding framing bits but including fcs octets). mstat counter write address = 0x2d 0x21c8 low 0x21c9 mid 0x21ca high transmittedframes65to127octets the total number of frames (includi ng bad frames) transmitted that were between 65 and 127 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x2e 0x21cc low 0x21cd mid 0x21ce high transmittedframes128to255octets the total number of frames (includi ng bad frames) transmitted that were between 128 and 255 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x2f 0x21d0 low 0x21d1 mid 0x21d2 high transmittedframes256to511octets the total number of frames (includi ng bad frames) transmitted that were between 256 and 511 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x30
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 214 document no.: pmc-2001304, issue 7 mstat counter registers read address 0x21d4 low 0x21d5 mid 0x21d6 high transmittedframes512to1023octets the total number of frames (includi ng bad frames) transmitted that were between 512 and 1023 octets in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x31 0x21d8 low 0x21d9 mid 0x21da high transmittedframes1024to1518octets the total number of frames (includi ng bad frames) transmitted that were between 1024 and (1518 octets for untagged frames and 1522 octets for vlan tagged frames) in length inclusive (excluding framing bits but including fcs octets). mstat counter write address = 0x32 0x21dc low 0x21dd mid 0x21de high transmittedframes1519tomaxoctets the total number of frames (includi ng bad frames) transmitted that were between the normal maximum length (1518 octets for un-tagged frames and 1522 octets for tagged frames) and the max jumbo frame length (i.e. up to maxframesize) (excluding framing bits but including fcs octets). mstat counter write address = 0x33 0x21e0 low 0x21e1 mid 0x21e2 high jumbooctetstransmittedok the total number of octets (excluding bad frames) transmitted that were between the normal maximum length (1518 octets for un-tagged frames and 1522 octets for tagged frames) and the max jumbo frame length (i.e. up to maxframesize) (excluding framing bits but including fcs octets). mstat counter write address = 0x34
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 215 document no.: pmc-2001304, issue 7 register 0x2200h:iflx global configuration register bit type function default bit 15 r/w ircu_enable 0 bit 14 r/w idswt_enable 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 ircu_enable the enable bit must be set to enable the operation of the ircu block. clearing this bit causes the entire ircu block to freeze and stop processing requests from either the write datapath or the system scheduler. idswt_enable the enable bit must be set to enable the operation of the idswt block. this bit must be set to a logic ?1? at all times.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 216 document no.: pmc-2001304, issue 7 register 0x2201h:iflx channel provision bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w prov[0] 0 prov the channel provision bit (prov) specifies the active status of the channel being accessed. when prov is asserted high, the channel is active. when prov is asserted low, the channel is inactive and is not used. the pr ov bit is used for enabling and disabling the single channels within the iflx, as well as to initialize the data and tag ram read/write addresses. a transition from the channel being active (prov is logic 1) to inactive (prov is logic 0) will reset the rate adaptation buffer, the frame buffer and freeze the logical fifo. a transition from the channel being inactive (prov is logic 0) to active (prov is logic 1) will reset the logical fifo read/write pointers to an empty state and begin to process data independent of other provisioned channels. a zer o value in this register will disable the channel, rendering it inactive. in the case of the pm3392 the only valid value is 0x0001h.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 217 document no.: pmc-2001304, issue 7 register 0x2209h:iflx fifo overflow enable bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 218 document no.: pmc-2001304, issue 7 register 0x220ah:iflx fifo overflow interrupt bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r reserved 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 219 document no.: pmc-2001304, issue 7 register 0x220dh:iflx indirect channel address bit type function default bit 15 r busy 0 bit 14 r/w rwb 1 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r unused 0 bit 6 r unused 0 bit 5 r unused 0 bit 4 r unused 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 rwb the read/write bar (rwb) bit selects between an update operation (write) and a query operation (read). writing logic 0 to rwb tri ggers the update operation with the information in the iflx indirect registers (0x220e to 0x2217). writing a logic 1 to rwb triggers a query and the information is placed in all of the iflx indirect registers. busy the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when a write to the indirect channel select register triggers an indirect access and will stay high until the access is complete. this register should be polled to determine when data from an indirect read operation is availabl e in all the indirect data registers or to determine when a new indirect write operation may commence.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 220 document no.: pmc-2001304, issue 7 register 0x220eh:iflx indirect lo gical fifo low limit & provision bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r/w lolim[9] 0 bit 8 r/w lolim[8] 0 bit 7 r/w lolim[7] 0 bit 6 r/w lolim[6] 0 bit 5 r/w lolim[5] 0 bit 4 r/w lolim[4] 0 bit 3 r/w lolim[3] 0 bit 2 r/w lolim[2] 0 bit 1 r/w lolim[1] 0 bit 0 r/w lolim[0] 0 lolim[9:0] the lower address boundary (lolim[9:0]) specifies the lower address limit in the ring buffer for the logical fifo defined in the indirect channel address register. the address value specified is in units of 256 bytes, or 16 128-bit words, and must point to the first byte of the first location in the ram that belongs to the fifo. for example, to set up a logical fifo with 4096 bytes of space lying betw een locations 256 and 511 128-bit words (inclusive) in the ram, the lolim[9:0] field must be set to 16 decimal. this value should be programmed to zero.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 221 document no.: pmc-2001304, issue 7 register 0x220fh:iflx indirect logical fifo high limit bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r/w hilim[9] 0 bit 8 r/w hilim[8] 0 bit 7 r/w hilim[7] 0 bit 6 r/w hilim[6] 0 bit 5 r/w hilim[5] 0 bit 4 r/w hilim[4] 0 bit 3 r/w hilim[3] 0 bit 2 r/w hilim[2] 0 bit 1 r/w hilim[1] 0 bit 0 r/w hilim[0] 0 hilim[9:0] the upper address boundary, (hilim[9:0]) specifies the upper address limit in the ring buffer for the logical fifo defined in the indi rect channel address register. hilim[9:0] is specified in units of 256 bytes, or 16 128-bit words, and must point to the first byte after the last ram location for the fifo. for example, to set up a logical fifo with 4096 bytes of space lying between locations 256 and 511 1 28-bit words (inclusive) in the ram, the hilim[9:0] field must be set to 32 decimal.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 222 document no.: pmc-2001304, issue 7 register 0x2210h:iflx indirect full/almost full status & limit bit type function default bit 15 r full 0 bit 14 r afull 0 bit 13 r/w afth[13] 0 bit 12 r/w afth[12] 0 bit 11 r/w afth[11] 0 bit 10 r/w afth[10] 0 bit 9 r/w afth[9] 0 bit 8 r/w afth[8] 0 bit 7 r/w afth[7] 0 bit 6 r/w afth[6] 0 bit 5 r/w afth[5] 0 bit 4 r/w afth[4] 0 bit 3 r/w afth[3] 0 bit 2 r/w afth[2] 0 bit 1 r/w afth[1] 0 bit 0 r/w afth[0] 0 afth [13:0] the almost full threshold field (afth[13:0]) is the number of 128-bit words that can be held in the logical fifo before the afull si gnal is asserted for the specified channel in the indirect channel address register. the afull signal is reported to the upstream datapath through the line side interface. when the num ber of 128-bit words held in this fifo (as measured by the word counter) is equal to or greater than afth[13:0], the afull output from the asserted, otherwise afull is de-asserte d. it is recommended that afth[13:0] be written only at initialization time. afull the almost full status bit (afull) is set wh en the number of words within the logical fifo is greater than the afth[13:0] value. this status information is provided for diagnostic purposes. full the full status bit (full) is set when the l ogical fifo is reporting a full status to the upstream write datapath. this status info rmation is provided for diagnostic purposes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 223 document no.: pmc-2001304, issue 7 register 0x2211h:iflx indirect em pty/almost empty status & limit bit type function default bit 15 r empty 1 bit 14 r aempty 1 bit 13 r/w aeth[13] 0 bit 12 r/w aeth[12] 0 bit 11 r/w aeth[11] 0 bit 10 r/w aeth[10] 0 bit 9 r/w aeth[9] 0 bit 8 r/w aeth[8] 0 bit 7 r/w aeth[7] 0 bit 6 r/w aeth[6] 0 bit 5 r/w aeth[5] 0 bit 4 r/w aeth[4] 0 bit 3 r/w aeth[3] 0 bit 2 r/w aeth[2] 0 bit 1 r/w aeth[1] 0 bit 0 r/w aeth[0] 0 aeth [13:0] the almost empty threshold field (aeth[13:0]) is the number of 128-bit words that are held in the logical fifo before the afull si gnal is de-asserted. the aempty signal is reported to the upstream datapath through the line side interface. when the number of 128- bit words held in this fifo (as measured by the word counter) is equal to or less than aeth[13:0], the aempty output is asserted, ot herwise aempty is de-asserted. it is recommended that aeth[13:0] be written only at initialization time. aempty the almost empty status bit (aempty) is set when the number of words within the logical fifo is less than or equal to the aeth[13:0] va lue. this status information is provided for diagnostic purposes. empty the empty status bit (empty) is set whenever the logical fifo is completely empty. this flag is provided for diagnostic purposes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 224 document no.: pmc-2001304, issue 7 register 0x2240h:pl4mos configuration register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r/w re_init 0 bit 2 r/w pl4mos_en 0 bit 1 r/w no_status 0 bit 0 r/w reserve 1 no_status the no_status bit is set to 1 to indicate that status information is not available. in this case, infinite credit is assigned. when no_s tatus bit is set to 0, the pl4 status information is available and the pl4mos may use it to implement the credit based scheduling algorithm. no_status bit should be updated before enabling the pl4mos (pl4mos_en). note: if the no_status bit is set to 1 th en for proper operation the pl4io no_istat bit, in the pl4io configuration register 0x2305h, must also be set to 1. if not then the mac?s can overflow their respective fifo ?s due to improper calendar operation. pl4mos_en when the pl4mos_en bit is set low, the pl4 mos is disabled and no traffic can be passed. when the pl4mos_en bit is set high, the pl4mos operates in normal mode. changing this bit does not affect the internal status or counters of the pl4mos. this bit should be set high after the iflx and eflx have been in itialized. if the upstream logic has to be reconfigured during normal operation, th e pl4mos_en bit should be low and the re_init bit should be high to clear all the internal counters and previous status. for diagnostic purposes, this bit should be set lo w to disable the pl4mos before reading the internal status registers. this guara ntees the consistency of the data read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 225 document no.: pmc-2001304, issue 7 re_init re_init bit is used to clear all the internal status registers. it does not affect the configuration registers. when the re_init bit is set high, all the internal counters and status calendar are reset to 0. when it is set low, the pl4mos operates in normal mode.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 226 document no.: pmc-2001304, issue 7 register 0x2241h:pl4mos reserved bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 reserved this register should be programmed to zero at all times.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 227 document no.: pmc-2001304, issue 7 register 0x2242h:pl4mos fairness mask bit type function default bit 15 r/w reserved 1 bit 14 r/w reserved 1 bit 13 r/w reserved 1 bit 12 r/w reserved 1 bit 11 r/w reserved 1 bit 10 r/w reserved 1 bit 9 r/w reserved 1 bit 8 r/w reserved 1 bit 7 r/w reserved 1 bit 6 r/w reserved 1 bit 5 r/w reserved 1 bit 4 r/w reserved 1 bit 3 r/w reserved 1 bit 2 r/w reserved 1 bit 1 r/w reserved 1 bit 0 r/w reserved 1 pl4mos fairness mask register this register should be programmed to zero at all times.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 228 document no.: pmc-2001304, issue 7 register 0x2243h:pl4mos maxburst1 register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r/w max_burst1[11] 0 bit 10 r/w max_burst1[10] 0 bit 9 r/w max_burst1[9] 0 bit 8 r/w max_burst1[8] 0 bit 7 r/w max_burst1[7] 0 bit 6 r/w max_burst1[6] 0 bit 5 r/w max_burst1[5] 0 bit 4 r/w max_burst1[4] 0 bit 3 r/w max_burst1[3] 1 bit 2 r/w max_burst1[2] 0 bit 1 r max_burst1[1] 0 bit 0 r max_burst1[0] 0 max_burst1 max_burst1 defines the amount of credit, in 128-bit words, granted for a starving channel. this value depends on the system late ncy and architecture. note that the lower 2 bits are forced to zero in order to constrai n max_burst1 to modulo 4 values. the default value is 8 words; i.e. 128 bytes. pl4mos_en bit should be deasserted before writing to this register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 229 document no.: pmc-2001304, issue 7 register 0x2244h:pl4mos maxburst2 register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r/w max_burst2[11] 0 bit 10 r/w max_burst2[10] 0 bit 9 r/w max_burst2[9] 0 bit 8 r/w max_burst2[8] 0 bit 7 r/w max_burst2[7] 0 bit 6 r/w max_burst2[6] 0 bit 5 r/w max_burst2[5] 0 bit 4 r/w max_burst2[4] 0 bit 3 r/w max_burst2[3] bit 2 r/w max_burst2[2] 0 bit 1 r max_burst2[1] 0 bit 0 r max_burst2[0] 0 max_burst2 max_burst2 defines the amount of credit, in 128-bit words, granted for a hungry channel. this value depends on the system late ncy and architecture. note that the lower 2 bits are forced to zero in order to constrai n max_burst2 to modulo 4 values. the default value is 8 words; i.e. 128 bytes. pl4mos_en bit should be deasserted before writing to this register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 230 document no.: pmc-2001304, issue 7 register 0x2245h:pl4mos transfer size register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r/w max_transfer[7] 0 bit 6 r/w max_transfer[6] 0 bit 5 r/w max_transfer[5] 0 bit 4 r/w max_transfer[4] 0 bit 3 r/w max_transfer[3] 1 bit 2 r/w max_transfer[2] 0 bit 1 r max_transfer[1] 0 bit 0 r max_transfer[0] 0 max_transfer max_transfer defines the maximum number of 128-bit words that may be transferred during one service request. note that the lower 2 b its are forced to zero in order to constrain max_transfer to modulo 4 values. pl4mos_en bit should be deasserted before writing to this register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 231 document no.: pmc-2001304, issue 7 register 0x2280h:pl4odp configuration bit type function default bit 15 r/w repeat_t[3] 0 bit 14 r/w repeat_t[2] 0 bit 13 r/w repeat_t[1] 0 bit 12 r/w repeat_t[0] 0 bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r/w sop_rule 1 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r unused x bit 3 r unused x bit 2 r reserved 0 bit 1 r/w en_ports 0 bit 0 r/w en_dfwd 0 en_dfwd enable data forward. when ?1?, data will be forwarded. when ?0?, data will not be forwarded. modifying this register bit dur ing packet data reception can result in the creation of partial packets en_ports enable port. when ?1?, data will be forwarded. when ?0?, data will not be forwarded by the pl4odp. this bit only takes effect on packet boundaries. no partial packets can be created. sop_rule the value of sop_rule determines the minimum number of pl4 bus cycles between successive start-of-packet control words. sop_rule minimum sop spacing (in terms of pl4 bus cycles) 0 2 1 8
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 232 document no.: pmc-2001304, issue 7 repeat_t[3:0] repeat_t is the pl4 bus configuration pa rameter defining how many back-to-back training patterns define a training sequence. th e value of this input is actually the number of training patterns plus one: a value of repeat_t of 0x0 means that a single 20-cycle (pl4 bus cycle) training pattern defines a training sequence; a value of 0xf for repeat_t implies that the training sequence will be 320-cycles, with the 20-cycle training pattern repeated 16 times consecutively.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 233 document no.: pmc-2001304, issue 7 register 0x2282h:pl4odp interrupt mask bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r/w 0 bit 6 r/w 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w 0 bit 2 r/w 0 bit 1 r/w 0 bit 0 r/w out_dise 0 out_dise the out_dise bit enables the generation of an interrupt due to the primary input signal out_dis being deasserted when the link state is pl4odp_fwd.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 234 document no.: pmc-2001304, issue 7 register 0x2283h:pl4odp interrupt bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r unused x:high bit 7 r 0 bit 6 r 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r 0 bit 2 r 0 bit 1 r 0 bit 0 r out_disi 0 out_disi the out_disi bit will be set when the primar y input signal out_dis is deasserted when the link state is pl4odp_fwd. if out_dise is ?1? in the pl4odp interrupt mask register, an interrupt will also be generated (int output asserted).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 235 document no.: pmc-2001304, issue 7 register 0x2284h:pl4odp configuration max_t register bit type function default bit 15 r/w max_t[15] 0 bit 14 r/w max_t[14] 0 bit 13 r/w max_t[13] 0 bit 12 r/w max_t[12] 0 bit 11 r/w max_t[11] 0 bit 10 r/w max_t[10] 0 bit 9 r/w max_t[9] 0 bit 8 r/w max_t[8] 0 bit 7 r/w max_t[7] 0 bit 6 r/w max_t[6] 0 bit 5 r/w max_t[5] 0 bit 4 r/w max_t[4] 1 bit 3 r/w max_t[3] 0 bit 2 r/w max_t[2] 0 bit 1 r/w max_t[1] 0 bit 0 r/w max_t[0] 0 max_t[15:0] max_t defines the bounded interval in time ove r which the pl4 training sequence is to be sent. the time value of max_t is given in terms of 16 internal clk cycles. max_t setting of 0x000 has a special meaning notes: the maximum value in time defined by max_t for a pl4 cycle frequency of 833 mhz is: (2**16)*(16 clk cycles)*(4/833 mhz per clk cycle) = 5.0 ms. for a 700 mhz clock this is about 6 ms. a value of 0x000 for max_t will result in di sabling the timer associated with the sending of training patterns. when the max_t register is set to 0x000, and the out_dis input is deasserted, no training patterns will be sent from the pl4odp. if out_dis is asserted, the pl4odp transmits idle patterns regardless of the value of max_t. default value of 16 in max_t for a pl4 cycle frequency of 833 mhz means that a training sequence will occur every (16)*(16 clk cycles)*(4/833 mhz per clk cycle) = 1.23 us. for a 700 mhz clock this is 1.46 us.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 236 document no.: pmc-2001304, issue 7 the pm3392 waits until the current data transfer is complete before transmitting a training sequence when the max_t timer expires. this may result in intervals greater than max_t between successive training sequences when data throughput is high. furthermore, it may result in an average interval between trai ning sequences greater than max_t over a long period of time. if a system has a minimum value for this interval that is critical for correct operation, then max_t should be set lower than the minimum value. the required setting depends on data transfer size and pl4 ingress path bandwidth utiliza tion. a guardband of 5% should be sufficient
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 237 document no.: pmc-2001304, issue 7 register 0x2300h:pl4io lock detect status bits type function default 15 r out_rool 1 14 r unused x 13 r unused x 12 r is_rool 1 11 r dip2_err x 10 r unused x 9 r unused x 8 r id_rool 1 7 r unused x 6 r unused x 5 r unused x 4 r is_dool 1 3 r unused x 2 r unused x 1 r unused x 0 r id_dool 1 the current reference out of lock (rool) a nd data out of lock (dool) conditions for the pl4 interface. id_dool depending on the setting of the dlsel bit in th e pl4io configuration register, either the input data fifos are not aligned to the inco ming data stream (in normal operation) or a valid prbs pattern is not being received in the input data fifos (in serial data link testing.) is_dool the parallel fifo status input stream is not properly synchronized. dip2_err a dip2 error occurred on the fifo status input stream. id_rool the parallel data input clock (tdclk) or one or more of the parallel data input streams is not trained to the local synthesized clock. the pl4 data input interface is normally disabled when id_rool is asserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 238 document no.: pmc-2001304, issue 7 is_rool the input fifo status clock (rsclk) frequency exceeds ? the frequency of rdclk. the pl4 input status interface is normally disabled when is_rool is asserted. out_rool the local synthesized clock is not trained to the reference frequency. the pl4 data and status output interfaces are normally disabled when out_rool is asserted. all of the pl4io interfaces share a single clock synthesizer.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 239 document no.: pmc-2001304, issue 7 register 0x2301h:pl4io lock detect change bits type function default 15 r out_rooli 0 14 r unused x 13 r unused x 12 r is_rooli 0 11 r dip2_erri x 10 r unused x 9 r unused x 8 r id_rooli 0 7 r unused x 6 r unused x 5 r unused x 4 r is_dooli 0 3 r unused x 2 r unused x 1 r unused x 0 r id_dooli 0 indicates whether any of the reference out of lock (rool) or data out of lock (dool) conditions on the pl4 interface have changed si nce the previous ecbi read from the lock detect change register. an interrupt request (rool_int or dool_int) will be asserted when any pair of corresponding bits in the lock detect change and lock detect mask registers are both set to logic "1". id_dooli the input data out of lock condition has changed. id_dooli is set to logic "1" when the value of the id_dool condition changes. is_dooli the input status out of lock condition has changed. is_dooli is set to logic "1" when the value of the is_dool condition changes. id_rooli the input data reference out of lock condition has changed. id_rooli is set to logic "1" when the value of the id_rool condition changes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 240 document no.: pmc-2001304, issue 7 dip2_erri the dip2_erri status condition has changed. dip2_erri is set to logic "1" when the value of the dip2_err condition changes. is_rooli the input status reference out of lock condition has changed. is_rooli is set to logic "1" when the value of the is_rool condition changes. out_rooli the output reference out of lock condition has changed. out_rooli is set to logic "1" when the value of the out_rool condition changes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 241 document no.: pmc-2001304, issue 7 register 0x2302h:pl4io lock detect mask bits type function default 15 r/w out_roole 0 14 r unused x 13 r unused x 12 r unused x 12 r/w is_rool 0 11 r dip2_erre x 10 r unused x 9 r unused x 8 r/w id_roole 0 7 r unused x 6 r unused x 5 r unused x 4 r/w is_doole 0 3 r unused x 2 r unused x 1 r unused x 0 r/w id_doole 0 arms the pl4io interrupt requests (rool_int and dool_int) when any pair of corresponding bits in the lock detect change a nd lock detect mask registers are both set to logic "1". id_doole enables the triggering of dool_int. the dool_int signal is asserted when the id_dool bits in the lock detect change and lock detect mask registers are both set to logic "1". is_doole enables the triggering of dool_int. the dool_int signal is asserted when the is_dool bits in the lock detect change and lock detect mask registers are both set to logic "1". id_roole enables the triggering of rool_int. the rool_int signal is asserted when the id_rool bits in the lock detect change and lock detect mask registers are both set to logic "1".
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 242 document no.: pmc-2001304, issue 7 dip2_erre enables the triggering of dip2_err interrupt. the dip2_err interrupt signal is asserted when the dip2_err bits in the lock detect change and lock detect mask registers are both set to logic "1". is_roole enables the triggering of rool_int. the rool_int signal is asserted when the is_rool bits in the lock detect change and lock detect mask registers are both set to logic "1". out_roole enables the triggering of rool_int. the rool_int signal is asserted when the out_rool bits in the lock detect change and lock detect mask registers are both set to logic "1".
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 243 document no.: pmc-2001304, issue 7 register 0x2303h:pl4io lock detect limits bits type function default 15 r/w ref_limit[7] 0 14 r/w ref_limit[6] 0 13 r/w ref_limit[5] 0 12 r/w ref_limit[4] 0 11 r/w ref_limit[3] 0 10 r/w ref_limit[2] 0 9 r/w ref_limit[1] 0 8 r/w ref_limit[0] 1 7 r/w tran_limit[7] 0 6 r/w tran_limit[6] 0 5 r/w tran_limit[5] 1 4 r/w tran_limit[4] 1 3 r/w tran_limit[3] 1 2 r/w tran_limit[2] 1 1 r/w tran_limit[1] 1 0 r/w tran_limit[0] 1 specifies the permitted range of measured clock frequency deviation, relative to the selected reference clock. ref_limit[7:0] the maximum permitted deviation for any cloc k derived from the reference clock, in multiples of 30 ppm (nominal - 30.773 ppm actual). ref_limit applies to the csu and to the input data clock (idclk). ref_limit is set to logic "0000_0001" (30 ppm nominal) when drstb is asserted. tran_limit[7:0] the minimum number of input data transition events (in multiples of 16) required to synchronize the dru to the incoming data stream. tran_limit applies to the drus. tran_limit is set to logic "0011_1111" (1024 transitions) when drstb is asserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 244 document no.: pmc-2001304, issue 7 register 0x2304h:pl4io calendar repetitions bits type function default 15 r/w in_mul[7] 0 14 r/w in_mul[6] 0 13 r/w in_mul[5] 0 12 r/w in_mul[4] 0 11 r/w in_mul[3] 0 10 r/w in_mul[2] 0 9 r/w in_mul[1] 0 8 r/w in_mul[0] 0 7 r/w out_mul[7] 0 6 r/w out_mul[6] 0 5 r/w out_mul[5] 0 4 r/w out_mul[4] 0 3 r/w out_mul[3] 0 2 r/w out_mul[2] 0 1 r/w out_mul[1] 0 0 r/w out_mul[0] 0 specifies the number of repetitions in the fifo status calendars. in_mul[7:0] the number of repetitions of the input fifo status channel within a complete status calendar sequence. the pl4 input status parameter calendar_m = in_mul + 1. the total length of the input status cale ndar sequence = calendar_len x calendar_m. in_mul should only be changed while the input status interface is disabled in the configuration register. the result of cha nging in_mul while the status interface is enabled is unspecified. out_mul[7:0] the number of repetitions of the output fifo st atus channels within a complete status calendar sequence. the pl4 output status parameter calendar_m = out_mul + 1. the total length of the output status calendar sequence = calendar_len x calendar_m. out_mul should only be changed while the output status interface is disabled in the configuration register. the result of cha nging out_mul while the status interface is enabled is unspecified.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 245 document no.: pmc-2001304, issue 7 register 0x2305h:pl4io configuration bits type function default 15 r/w dip2err_ch k 0 14 r/w reset 0 13 r/w iddq 0 12 r/w enable 1 11 r/w odat_dis x 10 r/w train_dis x 9 r/w ostat_dis 1 8 r/w istat_dis 1 7 r/w no_istat 0 6 r/w stat_outse l x 5 r/w insel 0 4 r/w dlsel 0 3 reserved x 2 reserved x 1 r/w outsel[1] 0 0 r/w outsel[0] 1 specifies the requested configuration of the pl4 io interface. in normal operation the pl4io control logic will sequence the internal pl4i o components toward this configuration. outsel[1:0] selects the source of the 68 bit parallel data stream for the pisos. 00 ? none 01 ? pl4odp output data stream (outd[67:0]) ? normal mode 10 ? prbs generate data stream ? used for pl4 data link testing 11 ? fifo read data stream enables pl 4 system-side (local) loopback. data is looped- back from the device tctl and tdat[15:0] input pins to the rctl and rdat[15:0] output pins. outsel is set to logic "01" when drstb is asserted.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 246 document no.: pmc-2001304, issue 7 dlsel selects the source for the input data out of lock (id_dool) condition. 0 ? the input data fifos are not aligned to the incoming data stream ? used for normal parallel data link operation 1 ? a valid prbs pattern is not being received in the input data fifos ? used for serial data link testing insel selects the source of the 68 bit parallel data stream for the unpacker (ind[67:0]), together with related handshake signals. 0 ? dru input data stream 1 ? packer output data stream (outd[67:0]) ? enables device-side (local) loopback ? the following connections are looped back: ? out_dis is driven from in_dis ? ins is driven from outs ? ind_valid is driven from outd_valid ? ind is driven from outd if pl4io insel is logic 1 (remote loopb ack from pl4odp to pl4idu) and pl4io outsel[1:0] is b01 (normal operation) data will be impressed on the pl4 rdat[15:0], rctl pins. if the user would like to disable the transfer of data on the pl4 rdat[15:0],rctl interface pins then the following can be done: step_1: program pl4io outsel[1:0 ] to b00. this will result in the rdat[15:0],rctl pins being driven to a logic 0. step_2: pl4io insel can be programmed to logic 1 to configure the pl4 interface for remote loopback. note: when insel is set to 1 the pl4 interface must be in master mode and have a valid reference clock for the loopback operation to work properly. the pl4io lock status logic continues to check the lock status on the devi ce?s pl4 interface pins. this will not effect the remote loopback operation even if the pl4 io reports is/id rool/dool out-of-lock, it means the pl4 partner is not configured or present.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 247 document no.: pmc-2001304, issue 7 stat_outsel selects the source of the output status impressed on the device tstat[1:0] output pins. 0 ? pl4io output status state machine (normal operation) 1 ? rstat input pins (pl4 local loopback operation) stat_outsel is set to logic 0 when drstb is asserted. no_istat when no_istat is cleared to logic "0" the input fifo status channel operates normally. when no_istat is set to logic "1" the input fifo status channel is disabled and the rstat pins are ignored. the output data path can operate normally while no_istat is set to logic "1" and istat_dis is cleared to logic "0". this bit should not be set until the output data path has been configured for normal operation. note: if the no_istat bit is set to 1 then for proper operation the pl4mos no_status bit, in the pl4mos configuration register 0x2240h, must also be set to 1. if not then the mac?s can overflow their r espective fifo?s due to improper calendar operation. istat_dis when istat_dis is cleared to logic "0" the input fifo status channel operates normally. when istat_dis is set to logic "1" the input fifo status channel is disabled and the rstat pins are ignored. neither the output data path nor the input status path will operate normally while istat_dis is set to logic "1". istat_dis is set to logic "1" when drstb is asserted. this bit should not be cleared until the output data path and input status path have been configured for normal operation. this bit should not be cleared in slave mode un til the input data clock (idclk) is valid. ostat_dis when ostat_dis is cleared to logic "0" the output fifo status channel operates normally. when ostat_dis is set to logic "1" the output fifo status channel is disabled and the ostat pins are driven high. the input data path can operate normally while ostat_dis is set to logic "1". ostat_dis is set to logic "1" when drstb is asserted. this bit should not be cleared until the input data path and output status path have been configured for normal operation. this bit should not be cleared in slave mode until the input data clock (idclk) is valid.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 248 document no.: pmc-2001304, issue 7 train_dis when train_dis is cleared to logic "0" th e pl4 input data deskew function operates normally. when train_dis is set to logic "1" the input data deskew function is disabled and the pl4 training pattern is ignored. neither the input data path nor the output status path will operate normally while train_dis is set to logic "1". train_dis is cleared to logic "0" when drstb is asserted while refsel[0] is high (master mode). train_dis is loaded fr om refsel[1] when drstb is asserted while refsel[0] is low (slave mode). this bit s hould not be cleared in slave mode until the input data clock (idclk) is valid. odat_dis when odat_dis is cleared to logic "0" the output data bus (odat) operates normally. when odat_dis is set to logic "1" the output data bus is disabled and the octl / odat pins are driven low. the input status path can operate normally while odat_dis is set to logic "1". odat_dis is cleared to logic "0" when drstb is asserted while refsel[0] is high (master mode). odat_dis is loaded from refsel[1] when drstb is asserted while refsel[0] is low (slave mode). this bit s hould not be cleared in slave mode until the input data clock (idclk) is valid. enable when enable is set to logic "1" normal ope ration of the pl4io is enabled. when enable is cleared to logic "0" the pl4io is disabled and the enb signals to the abcs are deasserted to minimize power consumption. enable is set to logic "1" when drstb is asserted. iddq when iddq is set to logic "1" the common iddq signal to the pl4io analog block components (abcs) is asserted. this causes all digital abc outputs going to core logic to be held static and all abc circuitry powered fro m the core power supply to be held static. for normal operation iddq should be cleared to logic "0". reset when reset is set to logic "1" the pl4io c ontrol logic (?wrapper?) is initialized. the effect is nearly identical to asserting drstb to this tsb. the port configuration register itself is also initialized, except for the reset bit. reset does not reset the analog block components (abcs) of the pl4io.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 249 document no.: pmc-2001304, issue 7 dip2err_chk when dip2err_chk is set to logic ?1? the recei ve status state machine will go out of lock when an error occurs in con secutive frames. an error is defined as a dip2 error, a ?11? channel status, or missing an expected sync pa ttern. rev a returned to the hold state after an error when the next end of calendar was found. a bug this caused is that the state machine would not lose lock in the case of cons tant invalid dip2 fields. setting this bit changes the state machine. after one error is detected, the state machine will return to the hold state after two end of calendar are found without another error.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 250 document no.: pmc-2001304, issue 7 register 0x3040h:txxg configuration register 1 bit type function default bit 15 r/w txen0 0 bit 14 r unused x bit 13 r/w hostpause 0 bit 12 r/w ipgt[5] 0 bit 11 r/w ipgt[4] 0 bit 10 r/w ipgt[3] 1 bit 9 r/w ipgt[2] 1 bit 8 r/w ipgt[1] 0 bit 7 r/w ipgt[0] 0 bit 6 r unused bit 5 r/w 32bit_align 0 bit 4 r/w crcen 0 bit 3 r/w fctx 0 bit 2 r/w fcrx 0 bit 1 r/w paden 0 bit 0 r reserved 0 paden if set, the txxg will pad all ieee 802.3 transmitt ed frames that are less than the minimum size up to the minimum size that is programmed in the tx_minfr register. the minimum size is set by the transmit min frame size register. padding is done by inserting zero-filled octets between the end of the payload and the start of the fcs field. if an ieee 802.3 frame has a vlan tag inserted, it will be padded to the minimum size + 4 bytes. fcrx if set, the txxg will respond to transmit pausing requests from the rxxg when a proper pause frame is received; otherwise, the txxg ignores these signals and never interrupts the outgoing transmit stream. fctx if set, the txxg will respond to pause frame tr ansmit requests that come from either the ingress buffer almost full threshold or the ex ternal pause pin input; otherwise, the txxg ignores these signals and never injects pause frames into the transmit stream.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 251 document no.: pmc-2001304, issue 7 crcen if crcen is set then all frames transmitted will have a 4 byte crc appended. if crcen is not set, frames transmitted will not have a crc appended. note: mac control pause packets generated internally will always ha ve a valid crc appended, regardless of the setting of crcen. corrupt packets [error bit set] will always have a corrupt crc appended, regardless of the setting of crcen. 32bit_align if 32bit_align is set, the packet that is output to the line must start 32-bit aligned i.e. line_sop[15:0] can only occur in byte lanes [15], [11], [7] or [3]. this 32-bit alignment is for ieee 802.3ae only. as a requirement, this bit must always be programmed to 1. ipgt [5:0] back-to-back transmit ipg. this is a programmable field representing the ipg between back-to-back packets. this is the ipg paramete r used in full-duplex mode. set this field to the number of octets of ipg desired. a setting of 12 decimal represents the minimum ipg of 12 bytes. the ipg setting is a average setting due to the 32-bit alignment requirement. the ipg may be +/- 3 bytes from the programmed ipg, and on average the ipg is the programmed value. note: because of the 32-bit alignment requirement the minimum programmed ipg that will not cause errors is 8 bytes +/- 3 bytes. so the minimum allowed setting of ipgt is 0x08h. table 16 interpacket gap encoding ipgt[5:0] ipg in bytes ipgt[5:0] ipg in bytes 00h 0 20h 32 01h 1 21h 33 02h 2 22h 34 03h 3 23h 35 04h 4 24h 36 05h 5 25h 37 06h 6 26h 38 07h 7 27h 39 08h 8 28h 40 09h 9 29h 41 0ah 10 2ah 42 0bh 11 2bh 43 0ch 12 2ch 44 0dh 13 2dh 45
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 252 document no.: pmc-2001304, issue 7 ipgt[5:0] ipg in bytes ipgt[5:0] ipg in bytes 0eh 14 2eh 46 0fh 15 2fh 47 10h 16 30h 48 11h 17 31h 49 12h 18 32h 50 13h 19 33h 51 14h 20 34h 52 15h 21 35h 53 16h 22 36h 54 17h 23 37h 55 18h 24 38h 56 19h 25 39h 57 1ah 26 3ah 58 1bh 27 3bh 59 1ch 28 3ch 60 1dh 29 3dh 61 1eh 30 3eh 62 1fh 31 3fh 63 hostpause hostpause enable bit. when this bit is set to a 1 the txxg will send pause control frames based on the pause timer and pause interval registers. the operation of hostpause is masked by fctx. txen0 this bit must be set to enable txxg to transmit packets. all txxg programming should be performed before setting this bit. if this bit is cleared during packet transmission, the current packet transmit will proceed to completion, and no new packet transmission initiated.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 253 document no.: pmc-2001304, issue 7 register 0x3042h:txxg configuration register 3 type function default bit 15 r/w fifo_erre 0 bit 14 r/w fifo_udre 0 bit 13 r/w max_lerre 0 bit 12 r/w min_lerre 0 bit 11 r/w xfere 0 bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r unused x bit 0 r unused x xfere the xfere bit enables the generation of an in terrupt when an accumulation interval is completed and new values are stored in the filter error counter holding register. when xfere is set to logic 1, the interrupt is enabled. min_lerre the min_lerre bit enables the generation of an interrupt for frames less than the minimum frame size programmed in the transmit min frame size register. max_lerre the max_lerre bit enables the generation of an interrupt for frames exceeding the maximum frame size programmed in the transmit max frame size register. fifo_udre the fifo_udre bit enables the generation of an interrupt due to a txxg fifo underrun event. when the fifo_erre bit is set to logic 1, an underrun event will cause the fifo_udri bit to be set in the interrupt register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 254 document no.: pmc-2001304, issue 7 fifo_erre the fifo_erre bit enables the generation of an interrupt due to a fifo error event. when the fifo_erre bit is set to logic 1, a fifo error event will cause the fifo_erri bit to be set in the interrupt register. fifo error events are: ? fifo_err asserted with fifo_eop. ? invalid sop/ eop sequence. ? invalid gapping during data transfer. ? frame length less than 14 bytes. ? fifo overrun.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 255 document no.: pmc-2001304, issue 7 register 0x3043h:txxg interrupt bit type function default bit 15 r fifo_erri 0 bit 14 r fifo_udri 0 bit 13 r max_lerri 0 bit 12 r min_lerri 0 bit 11 r xferi 0 bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r unused x bit 0 r unused x xferi the xferi bit indicates that a transfer of accumu lated counter data has occurred. a logic 1 in this bit position indicates that the filter erro r counter holding register has been updated. this update is initiated by writing to one of th e counter register locations, or by. if xfere is set in configuration register, then an interrupt will also be generated (int output asserted). the bit will clear on read. min_lerri the min_lerri bit is set for frames less th an the value programmed in the transmit min frame size register and if paden (bit 1 of the txxg configuration register 0x3040) is set to 0. if min_lerre is set in txxg configuration register 3, then an interrupt will also be generated (int output asser ted). the bit will clear on read. max_lerri the max_lerri bit is for frames exceeding the value programmed in the transmit max frame size register. if max_lerre is set in txxg configuration register 3, then an interrupt will also be generated (int out put asserted). the bit will clear on read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 256 document no.: pmc-2001304, issue 7 fifo_udri the fifo_udri bit is set when a fifo underrun event occurs. an underrun condition exists if the txxg is in the middle of tran smitting a packet and no additional data is available to be transmitted. if fifo_udre is set in txxg configuration register 2, then an interrupt will also be generated (int output asserted). the bit will clear on read. the fifo_erri bit is set when a fifo erro r event occurs. fifo error events are: ? fifo_err asserted with fifo_eop. ? invalid sop/ eop sequence. ? invalid gapping during data transfer. ? frame length less than 14 bytes. ? fifo overrun.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 257 document no.: pmc-2001304, issue 7 register 0x3044h:txxg status register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r unused x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r txactive 0 bit 0 r paused 0 paused when set, indicates that the pause timer is non-zero. this will happen whenever the rxxg interface transfers a non-zero pause value, or the cpu test mode loads a non-zero value, and the timer has not yet decremented to 0. txactive when set, indicates that the txxg is currently in the process of transmitting a packet from the system interface to the line interface, or is emitting a pause packet.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 258 document no.: pmc-2001304, issue 7 register 0x3045h:txxg tx_maxfr tr ansmit max frame size register bit type function default bit 15 r/w tx_maxfr[15] 0 bit 14 r/w tx_maxfr[14] 0 bit 13 r/w tx_maxfr[13] 0 bit 12 r/w tx_maxfr[12] 0 bit 11 r/w tx_maxfr[11] 0 bit 10 r/w tx_maxfr[10] 1 bit 9 r/w tx_maxfr[9] 0 bit 8 r/w tx_maxfr[8] 1 bit 7 r/w tx_maxfr[7] 1 bit 6 r/w tx_maxfr[6] 1 bit 5 r/w tx_maxfr[5] 1 bit 4 r/w tx_maxfr[4] 0 bit 3 r/w tx_maxfr[3] 1 bit 2 r/w tx_maxfr[2] 1 bit 1 r/w tx_maxfr[1] 1 bit 0 r/w tx_maxfr[0] 0 tx_maxfr[15:0] tx_maxfr[15:0] places an upper bound on a tr ansmitted ethernet frame, in octets. the length is measured from the first byte of the destination address to the last byte of the fcs field. the default is 0x05ee, corresponding to the standard setting of 1518 bytes or a maximum untagged ethernet frame. four byt es are automatically added for vlan tagged ethernet frames. maximum setting is 9600 bytes. if the pre-set frame length is exceeded by the frame source, the txxg unit will truncate the outgoing frame, force a crc error, and discard all subsequently received bytes until the next sof.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 259 document no.: pmc-2001304, issue 7 register 0x3046h:txxg tx_minfr transmit min frame size register bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r/w tx_minfr[7] 0 bit 6 r/w tx_minfr[6] 0 bit 5 r/w tx_minfr[5] 1 bit 4 r/w tx_minfr[4] 1 bit 3 r/w tx_minfr[3] 1 bit 2 r/w tx_minfr[2] 1 bit 1 r/w tx_minfr[1] 0 bit 0 r/w tx_minfr[0] 0 tx_minfr[7:0] the tx_minfr[7:0] field is used to set a lower limit on the size of a transmitted ethernet frame. the length is measured from the first byte of the destination address to the last byte of the payload, excluding the 4-byte fcs field. the default is set to 60 decimal, corresponding to the nominal 64-byte minimu m-size frame. if the txxg receives an ieee 802.3 frame (i.e., with the length/ type field set to 0x05dc or less) that is smaller than tx_minfr[7:0], and the paden bit is set in the txxg configuration register 1, it will pad the frame to tx_minfr[7:0] with zeros. paden must be enabled for frame sizes less than 32 bytes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 260 document no.: pmc-2001304, issue 7 register 0x3047h:txxg sa[15:0] station address bit type function default bit 15 r/w sa[15] 0 bit 14 r/w sa[14] 0 bit 13 r/w sa[13] 0 bit 12 r/w sa[12] 0 bit 11 r/w sa[11] 0 bit 10 r/w sa[10] 0 bit 9 r/w sa[9] 0 bit 8 r/w sa[8] 0 bit 7 r/w sa[7] 0 bit 6 r/w sa[6] 0 bit 5 r/w sa[5] 0 bit 4 r/w sa[4] 0 bit 3 r/w sa[3] 0 bit 2 r/w sa[2] 0 bit 1 r/w sa[1] 0 bit 0 r/w sa[0] 0 sa[15:0] the sa[15:0] register sets the low 16 bits of the 48-bit station address used for pause frame generation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 261 document no.: pmc-2001304, issue 7 register 0x3048h:txxg sa[31:16] station address bit type function default bit 15 r/w sa[31] 0 bit 14 r/w sa[30] 0 bit 13 r/w sa[29] 0 bit 12 r/w sa[28] 0 bit 11 r/w sa[27] 0 bit 10 r/w sa[26] 0 bit 9 r/w sa[25] 0 bit 8 r/w sa[24] 0 bit 7 r/w sa[23] 0 bit 6 r/w sa[22] 0 bit 5 r/w sa[21] 0 bit 4 r/w sa[20] 0 bit 3 r/w sa[19] 0 bit 2 r/w sa[18] 0 bit 1 r/w sa[17] 0 bit 0 r/w sa[16] 0 sa[31:16] the sa[31:16] register sets the middle 16 bits of the 48-bit station address used for pause frame generation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 262 document no.: pmc-2001304, issue 7 register 0x3049h:txxg sa[47:32] station address bit type function default bit 15 r/w sa[47] 0 bit 14 r/w sa[46] 0 bit 13 r/w sa[45] 0 bit 12 r/w sa[44] 0 bit 11 r/w sa[43] 0 bit 10 r/w sa[42] 0 bit 9 r/w sa[41] 0 bit 8 r/w sa[40] 0 bit 7 r/w sa[39] 0 bit 6 r/w sa[38] 0 bit 5 r/w sa[37] 0 bit 4 r/w sa[36] 0 bit 3 r/w sa[35] 0 bit 2 r/w sa[34] 0 bit 1 r/w sa[33] 0 bit 0 r/w sa[32] 0 sa[47:32] the sa[47:32] register sets the high 16 bits of the 48-bit station address used for pause frame generation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 263 document no.: pmc-2001304, issue 7 register 0x304dh:txxg pause_time ? pause timer register bit type function default bit 15 r/w pause_time[15] 1 bit 14 r/w pause_time [14] 1 bit 13 r/w pause_time [13] 1 bit 12 r/w pause_time [12] 1 bit 11 r/w pause_time [11] 1 bit 10 r/w pause_time [10] 1 bit 9 r/w pause_time [9] 1 bit 8 r/w pause_time [8] 1 bit 7 r/w pause_time [7] 1 bit 6 r/w pause_time [6] 1 bit 5 r/w pause_time [5] 1 bit 4 r/w pause_time [4] 1 bit 3 r/w pause_time [3] 1 bit 2 r/w pause_time [2] 1 bit 1 r/w pause_time [1] 1 bit 0 r/w pause_time [0] 1 pause_time [15:0] this register contains the pause timer value that is used on the pause control frames that are sent to the line interface. the default is 0xffff for an xon/xoff type of protocol. in diagnostic mode, this re gister must be programmed before diag_hostpause is toggled from 0 to 1. in normal mode, this register must be programmed before hostpause is toggled from 0 to 1.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 264 document no.: pmc-2001304, issue 7 register 0x304eh:txxg pause_ival pause timer interval register bit type function default bit 15 r/w pause_ival[15] 1 bit 14 r/w pause_ ival [14] 1 bit 13 r/w pause_ ival [13] 0 bit 12 r/w pause_ ival[12] 0 bit 11 r/w pause_ ival [11] 1 bit 10 r/w pause_ ival [10] 1 bit 9 r/w pause_ ival [9] 1 bit 8 r/w pause_ ival [8] 1 bit 7 r/w pause_ ival [7] 1 bit 6 r/w pause_ ival [6] 1 bit 5 r/w pause_ ival [5] 1 bit 4 r/w pause_ ival [4] 1 bit 3 r/w pause_ ival [3] 1 bit 2 r/w pause_ ival [2] 1 bit 1 r/w pause_ ival [1] 1 bit 0 r/w pause_ ival [0] 1 pause_ ival [15:0] this register contains the pause timer interval value that is used by the pause generation logic to control how often a pause control frame is sent. the pause_ival decrements every 512 bit times (pause quanta). the default value is 0xcfff.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 265 document no.: pmc-2001304, issue 7 register 0x3052h:txxg pause quantum value configuration register bit type function default bit 15 r/w unused x:high bit 14 r/w unused x:high bit 13 r/w unused x:high bit 12 r/w unused x:high bit 11 r/w unused x:high bit 10 r/w unused x:high bit 9 r/w unused x:high bit 8 r/w fc_phy_pace_en 0 bit 7 r/w fc_pause_qntm [7] 0 bit 6 r/w fc_pause_qntm [6] 0 bit 5 r/w fc_pause_qntm [5] 0 bit 4 r/w fc_pause_qntm [4] 0 bit 3 r/w fc_pause_qntm [3] 0 bit 2 r/w fc_pause_qntm [2] 1 bit 1 r/w fc_pause_qntm [1] 1 bit 0 r/w fc_pause_qntm [0] 1 fc_pause_qntm [7:0] the fc_pause_qntm [15:0] register indicates the number of sysclkx2 cycles that are to be used for scaling the pause_quantum value (m inus 1). a value of 7 means that every 8 sysclkx2 cycles, the local pause timer value decrements by 1. fc_phy_pace_en if fc_phy_pace_en is set, the local pause timer in the incoming_fc module will stall decrementing [when loaded] once in every 33 sysclkx2 cycles.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 266 document no.: pmc-2001304, issue 7 register 0x3080h:t64b66b configuration 1 bit type function default bit 15 r/w tip 0:high bit 14 r/w swave_len[2] 0:high bit 13 r/w swave_len[1] 0:high bit 12 r/w swave_len[0] 0:high bit 11 r unused 0:high bit 10 r unused 0:high bit 9 r unused 0:high bit 8 r/w jdat_pat_sel 0:high bit 7 r/w jtst_pat_sel 0:high bit 6 r/w jitt_pat_en 0:high bit 5 r/w rxerr_dis 0 bit 4 r/w reserved 0 bit 3 r/w 0 bit 2 r/w reserved 1 bit 1 r/w int_en 0 bit 0 r/w reserved int_en when ?1?, the interrupts are enabled. when ?0?, the interrupts are disabled. reserved this bit is reserved and must be programmed to 1. rx_errdis when ?1?, the t64b66b block will ignore all of the receiver detected error events: loss of signal (los), remote fault (rf), and local fault (lf). all data received from the upstream device will be processed as normal. the associated interrupts (rx_lfi, rx_rfi and rx_losi) will still assert even if the rx_errdis bit is set to ?1?. when ?0?, the t64b66b block will not ignore the receiver detected error events: loss of signal (los), remote fault (rf), local fault (lf). all data received from the upstream device will be processed as normal only if th e receiver is not indicating any error(s).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 267 document no.: pmc-2001304, issue 7 jitt_pat_en when ?1?, the t64b66b block will ignore all input data and transmit a jitter test pattern using the scrambler and the data defined by the jdat_pat_sel bit. when ?0? the t64bt66b transmits data normally. jtst_pat_sel when ?1? the square wave test pattern is used for jitter testing. in this mode the t64bt66b transmits a square wave which c onsists of 4 ? 11 alternating series of 1?s and 0?s where the 4 ? 11 is defined by the swave_len bits. when ?0? the pseudo random test pattern is u sed for jitter testing. the input to the scrambler is then defined by jdat_pat_sel and the seeds used are defined by the jitter test seed registers. jdat_pat_sel when ?1? the zeros data pattern is used for jitte r testing. if we are in pseudo random test pattern mode also, the input to the scrambler is all zeros. when ?0? the lf ordered set is used for jitter t esting. when jitt_pat_en is ?1? also the input to the scrambler is a constant lf. swave_len number of consecutive 0?s and 1?s that constitute the square wave generated when we are in square wave test pattern mode. the value is offset by 4 so that the range is from 4 ? 11 i.e. swave_len=000 means 4 0?s and 1?s. tip when read this bit indicates that a transfer is in progress of the status register 0x03h. when this bit is written to, a transfer of the status bits occurs.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 268 document no.: pmc-2001304, issue 7 register 0x3083h:t64b66b status bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r unused x bit 8 r unused x bit 7 r reserved 0 bit 6 r rx_lf 0 bit 5 r rx_rf 0 bit 4 r rx_los 0 bit 3 r fifo_unrun 0 bit 2 r fifo_ovrun 0 bit 1 r seq 0 bit 0 r sop 0 note: to update these status bits one must first write to the t64b66b tip bit (bit-15) in register 0x3080 t64b66b configuration 1. then a read can be performed to get the status. sop when ?1?, indicates that a non 32 bit aligned packet was received. when ?0?, indicates that only aligned packets were received. seq when ?1?, indicates that the t64b66b has detected a incorrect sop/eop or eop/sop sequence. when ?0?, indicates that the t64b66b has not detected any incorrect sop/eop or eop/sop sequences. fifo_ovrun when ?1?, indicates that the t64b66b?s fifo has experienced an overflow since the last status read. an overflow is set when the fifo is full and a write cycle is executed ahead of the next read cycle.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 269 document no.: pmc-2001304, issue 7 when ?0?, indicates that the t64b66b?s fifo has not experienced an overflow since the last status read. fifo_unrun when ?1?, indicates that the t64b66b?s fifo has experienced an under run since the last status read. an under run is set when the fifo is empty and a read cycle is executed ahead of the next write cycle. when ?0?, indicates that the t64b66b?s fifo has not experienced an overflow since the last status read. rx_los when ?1?, indicates that the t64b66 b block has received an external: receiver loss of signal (los) event a nd is still sending an rf message. when ?0?, indicates that the t64b 66b has not received an external: receiver loss of signal event and is cap turing data from the upstream device. rx_rf when ?1?, indicates that the t64b66b block has received an external: receiver remote fault (rf) event and is still sending an rf message. when ?0?, indicates that the t64b66 b has not received an external: receiver remote fault event and is capturing data from the upstream device. rx_lf when ?1?, indicates that the t64b66b block h as received an external: receiver local fault (lf) event and is still sending an idle message. when ?0?, indicates that the t64b66 b has not received an external: receiver local fault event and is capturing data from the upstream device.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 270 document no.: pmc-2001304, issue 7 register 0x3085h: jitter test seed a 3 bit type function default bit 15 r unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r/w jitt_seed_a[57] 0 bit 8 r/w jitt_seed_a[56] 0 bit 7 r/w jitt_seed_a[55] 0 bit 6 r/w jitt_seed_a[54] 0 bit 5 r/w jitt_seed_a[53] 0 bit 4 r/w jitt_seed_a[52] 0 bit 3 r/w jitt_seed_a[51] 0 bit 2 r/w jitt_seed_a[50] 0 bit 1 r/w jitt_seed_a[49] 0 bit 0 r/w jitt_seed_a[48] 0 jitt_seed_a[57:48] contains bits 57 down to 48 of the 58 bi t pseudo random jitter test pattern seed a. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 271 document no.: pmc-2001304, issue 7 register 0x3086h: jitter test seed a 2 bit type function default bit 15 r/w jitt_seed_a[47] 1 bit 14 r/w jitt_seed_a[46] 1 bit 13 r/w jitt_seed_a[45] 1 bit 12 r/w jitt_seed_a[44] 1 bit 11 r/w jitt_seed_a[43] 1 bit 10 r/w jitt_seed_a[42] 1 bit 9 r/w jitt_seed_a[41] 1 bit 8 r/w jitt_seed_a[40] 1 bit 7 r/w jitt_seed_a[39] 1 bit 6 r/w jitt_seed_a[38] 1 bit 5 r/w jitt_seed_a[37] 1 bit 4 r/w jitt_seed_a[36] 1 bit 3 r/w jitt_seed_a[35] 1 bit 2 r/w jitt_seed_a[34] 1 bit 1 r/w jitt_seed_a[33] 1 bit 0 r/w jitt_seed_a[32] 1 jitt_seed_a[47:32] contains bits 47 down to 32 of the 58 bi t pseudo random jitter test pattern seed a. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 272 document no.: pmc-2001304, issue 7 register 0x3087h: jitter test seed a 1 bit type function default bit 15 r/w jitt_seed_a[31] 1 bit 14 r/w jitt_seed_a[30] 1 bit 13 r/w jitt_seed_a[29] 1 bit 12 r/w jitt_seed_a[28] 1 bit 11 r/w jitt_seed_a[27] 1 bit 10 r/w jitt_seed_a[26] 1 bit 9 r/w jitt_seed_a[25] 1 bit 8 r/w jitt_seed_a[24] 1 bit 7 r/w jitt_seed_a[23] 1 bit 6 r/w jitt_seed_a[22] 1 bit 5 r/w jitt_seed_a[21] 1 bit 4 r/w jitt_seed_a[20] 1 bit 3 r/w jitt_seed_a[19] 1 bit 2 r/w jitt_seed_a[18] 1 bit 1 r/w jitt_seed_a[17] 1 bit 0 r/w jitt_seed_a[16] 1 jitt_seed_a[31:16] contains bits 31 down to 16 of the 58 bi t pseudo random jitter test pattern seed a. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 273 document no.: pmc-2001304, issue 7 register 0x3088h: jitter test seed a 0 bit type function default bit 15 r/w jitt_seed_a[15] 1 bit 14 r/w jitt_seed_a[14] 1 bit 13 r/w jitt_seed_a[13] 1 bit 12 r/w jitt_seed_a[12] 1 bit 11 r/w jitt_seed_a[11] 1 bit 10 r/w jitt_seed_a[10] 1 bit 9 r/w jitt_seed_a[9] 1 bit 8 r/w jitt_seed_a[8] 1 bit 7 r/w jitt_seed_a[7] 1 bit 6 r/w jitt_seed_a[6] 1 bit 5 r/w jitt_seed_a[5] 1 bit 4 r/w jitt_seed_a[4] 1 bit 3 r/w jitt_seed_a[3] 1 bit 2 r/w jitt_seed_a[2] 1 bit 1 r/w jitt_seed_a[1] 1 bit 0 r/w jitt_seed_a[0] 1 jitt_seed_a[15:0] contains bits 15 down to 0 of the 58 bit pseudo random jitter test pattern seed a. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 274 document no.: pmc-2001304, issue 7 register 0x3089h: jitter test seed b 3 bit type function default bit 15 r/w unused x bit 14 r unused x bit 13 r unused x bit 12 r unused x bit 11 r unused x bit 10 r unused x bit 9 r/w jitt_seed_b[57] 0 bit 8 r/w jitt_seed_b[56] 0 bit 7 r/w jitt_seed_b[55] 0 bit 6 r/w jitt_seed_b[54] 0 bit 5 r/w jitt_seed_b[53] 0 bit 4 r/w jitt_seed_b[52] 0 bit 3 r/w jitt_seed_b[51] 0 bit 2 r/w jitt_seed_b[50] 0 bit 1 r/w jitt_seed_b[49] 0 bit 0 r/w jitt_seed_b[48] 0 jitt_seed_b[57:48] contains bits 57 down to 48 of the 58 bi t pseudo random jitter test pattern seed b. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 275 document no.: pmc-2001304, issue 7 register 0x308ah: jitter test seed b 2 bit type function default bit 15 r/w jitt_seed_b[47] 1 bit 14 r/w jitt_seed_b[46] 1 bit 13 r/w jitt_seed_b[45] 1 bit 12 r/w jitt_seed_b[44] 1 bit 11 r/w jitt_seed_b[43] 1 bit 10 r/w jitt_seed_b[42] 1 bit 9 r/w jitt_seed_b[41] 1 bit 8 r/w jitt_seed_b[40] 1 bit 7 r/w jitt_seed_b[39] 1 bit 6 r/w jitt_seed_b[38] 1 bit 5 r/w jitt_seed_b[37] 1 bit 4 r/w jitt_seed_b[36] 1 bit 3 r/w jitt_seed_b[35] 1 bit 2 r/w jitt_seed_b[34] 1 bit 1 r/w jitt_seed_b[33] 1 bit 0 r/w jitt_seed_b[32] 1 jitt_seed_b[47:32] contains bits 47 down to 32 of the 58 bi t pseudo random jitter test pattern seed b. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 276 document no.: pmc-2001304, issue 7 register 0x308bh: jitter test seed b 1 bit type function default bit 15 r/w jitt_seed_b[31] 1 bit 14 r/w jitt_seed_b[30] 1 bit 13 r/w jitt_seed_b[29] 1 bit 12 r/w jitt_seed_b[28] 1 bit 11 r/w jitt_seed_b[27] 1 bit 10 r/w jitt_seed_b[26] 1 bit 9 r/w jitt_seed_b[25] 1 bit 8 r/w jitt_seed_b[24] 1 bit 7 r/w jitt_seed_b[23] 1 bit 6 r/w jitt_seed_b[22] 1 bit 5 r/w jitt_seed_b[21] 1 bit 4 r/w jitt_seed_b[20] 1 bit 3 r/w jitt_seed_b[19] 1 bit 2 r/w jitt_seed_b[18] 1 bit 1 r/w jitt_seed_b[17] 1 bit 0 r/w jitt_seed_b[16] 1 jitt_seed_b[31:16] contains bits 31 down to 16 of the 58 bi t pseudo random jitter test pattern seed b. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 277 document no.: pmc-2001304, issue 7 register 0x308ch: jitter test seed b 0 bit type function default bit 15 r/w jitt_seed_b[15] 1 bit 14 r/w jitt_seed_b[14] 1 bit 13 r/w jitt_seed_b[13] 1 bit 12 r/w jitt_seed_b[12] 1 bit 11 r/w jitt_seed_b[11] 1 bit 10 r/w jitt_seed_b[10] 1 bit 9 r/w jitt_seed_b[9] 1 bit 8 r/w jitt_seed_b[8] 1 bit 7 r/w jitt_seed_b[7] 1 bit 6 r/w jitt_seed_b[6] 1 bit 5 r/w jitt_seed_b[5] 1 bit 4 r/w jitt_seed_b[4] 1 bit 3 r/w jitt_seed_b[3] 1 bit 2 r/w jitt_seed_b[2] 1 bit 1 r/w jitt_seed_b[1] 1 bit 0 r/w jitt_seed_b[0] 1 jitt_seed_b[15:0] contains bits 15 down to 0 of the 58 b it pseudo random jitter test pattern seed b. note: these bits can only be written when jitte r pattern generation is turned off, i.e. jitt_pat_en is written low.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 278 document no.: pmc-2001304, issue 7 register 0x3200h:eflx global configuration bit type function default bit 15 r/w ercu_en 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r/w en_edswt 0 bit 6 r unused 0 bit 5 r unused 0 bit 4 r unused 0 bit 3 r unused 0 bit 2 r unused 0 bit 1 r unused 0 bit 0 r unused 0 ercu_en the ercu_en bit must be set for the normal operation edswt_en the edswt_en bit must be set for normal operation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 279 document no.: pmc-2001304, issue 7 register 0x3201h:eflx ercu global status bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r ovf_err 0 bit 12 r reserved 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r reserved 0 ovf_err when ovr_err is asserted the address register and fifo flag unit has detected an overflow (i.e., a write to a fifo that could not be performed because the fifo was completely full). the ovf_err status bit is cl eared when the offending channel status is read.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 280 document no.: pmc-2001304, issue 7 register 0x3202h:eflx indirect channel address bit type function default bit 15 r busy 0 bit 14 r/w rwb 1 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r unused 0 bit 6 r unused 0 bit 5 r unused 0 bit 4 r unused 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 reserved the reserved bits in this register must remain 0. rwb the read/write bar (rwb) bit selects between an update operation (write) and a query operation (read). writing logic 0 to rwb tri ggers the update operation with the information in indirect registers. writing a logic 1 to rwb triggers a query and the information is placed in all of the indirect registers. busy the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when a write to the indirect channel select register triggers an indirect access and will stay high until the access is complete. this register should be polled to determine when data from an indirect read operation is availabl e in all the indirect data registers or to determine when a new indirect write operation may commence.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 281 document no.: pmc-2001304, issue 7 register 0x3203h:eflx indirect logical fifo low limit bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r/w lolim[9] 0 bit 8 r/w lolim[8] 0 bit 7 r/w lolim[7] 0 bit 6 r/w lolim[6] 0 bit 5 r/w lolim[5] 0 bit 4 r/w lolim[4] 0 bit 3 r/w lolim[3] 0 bit 2 r/w lolim[2] 0 bit 1 r/w lolim[1] 0 bit 0 r/w lolim[0] 0 lolim[9:0] the lower address boundary of the ring buffer for the logical fifo. this value should remain zero.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 282 document no.: pmc-2001304, issue 7 register 0x3204h:eflx indirect logical fifo high limit bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r/w hilim[9] 0 bit 8 r/w hilim[8] 0 bit 7 r/w hilim[7] 0 bit 6 r/w hilim[6] 0 bit 5 r/w hilim[5] 0 bit 4 r/w hilim[4] 0 bit 3 r/w hilim[3] 0 bit 2 r/w hilim[2] 0 bit 1 r/w hilim[1] 0 bit 0 r/w hilim[0] 0 hilim[9:0] the upper address boundary, in units of 256 bytes, of the ring buffer for the logical fifo. in the pm3392, this should be programmed to 64 decimal or 40 hex.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 283 document no.: pmc-2001304, issue 7 register 0x3205h:eflx indirect full/almost-full status and limit bit type function default bit 15 r full 0 bit 14 r afull 0 bit 13 r/w afth[13] 0 bit 12 r/w afth[12] 0 bit 11 r/w afth[11] 0 bit 10 r/w afth [10] 0 bit 9 r/w afth [9] 0 bit 8 r/w afth [8] 0 bit 7 r/w afth [7] 0 bit 6 r/w afth [6] 0 bit 5 r/w afth [5] 0 bit 4 r/w afth [4] 0 bit 3 r/w afth [3] 0 bit 2 r/w afth [2] 0 bit 1 r/w afth [1] 0 bit 0 r/w afth [0] 0 afth [13:0] the afth [13:0] field holds the threshold, in terms number of 128-bit words currently present in the logical fifo before an almost-full status is reported. afth [13:0] should be written at initialization time (ercuen = ?0?) w ith the total number of words allocated to the logical fifo, minus 3 for the latency thro ugh the ercu block itself, minus the required amount for the latency in the system bus controller. it is not changed by the ercu. afull the almost full status bit (afull) is set wh en the number of words within the logical fifo is greater than the afth[13:0] value. this status information is provided for diagnostic purposes. full the full status bit (full) is set when the l ogical fifo is reporting a full status to the upstream write datapath. this status info rmation is provided for diagnostic purposes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 284 document no.: pmc-2001304, issue 7 register 0x3206h:eflx indirect empt y/almost-empty status and limit bit type function default bit 15 r empty 0 bit 14 r aempty 0 bit 13 r/w aeth[13] 0 bit 12 r/w aeth [12] 0 bit 11 r/w aeth[11] 0 bit 10 r/w aeth [10] 0 bit 9 r/w aeth [9] 0 bit 8 r/w aeth [8] 0 bit 7 r/w aeth [7] 0 bit 6 r/w aeth [6] 0 bit 5 r/w aeth [5] 0 bit 4 r/w aeth [4] 0 bit 3 r/w aeth [3] 0 bit 2 r/w aeth [2] 0 bit 1 r/w aeth [1] 0 bit 0 r/w aeth [0] 0 aeth [13:0] the aeth [13:0] field holds the threshold, in terms number of 128-bit words currently present in the logical before an almost-empty status is reported. aeth [13:0] should be written at initialization time (ercuen = ?0?) with a value greater than 0, but less than the total number of words allocated to the logi cal fifo. it is not changed by the ercu. aempty the almost empty status bit (aempty) is set when the number of words within the logical fifo is less than or equal to the aeth[13:0] va lue. this status information is provided for diagnostic purposes. empty the empty status bit (empty) is set whenever the logical fifo is completely empty. this flag is provided for diagnostic purposes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 285 document no.: pmc-2001304, issue 7 register 0x3207h:eflx indirect fifo cut-through threshold bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r/w cut_thru[13] 0 bit 12 r/w cut_thru [12] 0 bit 11 r/w cut_thru [11] 0 bit 10 r/w cut_thru [10] 0 bit 9 r/w cut_thru [9] 0 bit 8 r/w cut_thru [8] 0 bit 7 r/w cut_thru [7] 0 bit 6 r/w cut_thru [6] 0 bit 5 r/w cut_thru [5] 0 bit 4 r/w cut_thru [4] 0 bit 3 r/w cut_thru [3] 0 bit 2 r/w cut_thru [2] 0 bit 1 r/w cut_thru [1] 0 bit 0 r/w cut_thru [0] 0 cut_thru [13:0] the cut_thru [13:0] field holds the threshold, in terms number of 128-bit words currently present in the logical before a fr ame is released. it should be written at initialization time (ercu_en = ?0? and prov = ?1?) with the total number of words of a given frame that should be written for the logical fifo before reads are issued on the line side to minimize the probability of an underflow situation. it is not changed by the ercu. note: the eflx will begin transmitting when the fi ll level is within 208 bytes of the cut through threshold. also note that depending on traffic flow across the pl4 interface the value of the cut_thru register can cause transmit underruns in the transmit mac. please refer to section 13.13.1 in the operation section to help clarify the use of the cut_thru register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 286 document no.: pmc-2001304, issue 7 register 0x320ch:eflx fifo overflow error enable bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w ovfe 0 ovfe the overflow interrupt enable controls the assertion of the int output when ovfi. when ovfe is set high, an interrupt is generate d upon assertion event of the ovfi register. when ovfe is set low, changes in the ovf i status do not generate an interrupt.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 287 document no.: pmc-2001304, issue 7 register 0x320dh: eflx fifo overflow error indication bit type function default bit 15 r reserved 0 bit 14 r reserved 0 bit 13 r reserved 0 bit 12 r reserved 0 bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r reserved 0 bit 6 r reserved 0 bit 5 r reserved 0 bit 4 r reserved 0 bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r reserved 0 bit 0 r ovfi 0 ovfi the ovfi interrupt flag is set whenever an overflow (i.e., an attempted write to a completely full fifo) is detected. the ovfi register bit is cleared immediately after it is read
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 288 document no.: pmc-2001304, issue 7 register 0x3210h:eflx channel provision bit type function default bit 15 r/w reserved 0 bit 14 r/w reserved 0 bit 13 r/w reserved 0 bit 12 r/w reserved 0 bit 11 r/w reserved 0 bit 10 r/w reserved 0 bit 9 r/w reserved 0 bit 8 r/w reserved 0 bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w prov 0 prov the channel provision bit (prov) specifies th e active status of the channel being accessed. the pm3392 has only a single channel. when pr ov is asserted high, the channel is active. when prov is asserted low, the channel is inac tive and is not used. the prov bit is used for enabling and disabling the single channel within the eflx, as well as to initialize the data and tag ram read/write addresses. a tr ansition from the channel being active (prov is logic 1) to inactive (prov is logic 0) w ill reset the rate adaptation buffer and freeze the fifo. a transition from the channel being inac tive (prov is logic 0) to active (prov is logic 1) will latch in the lo_lim[9:0], hi_lim[9:0], afth[13:0], aeth[13:0] and cut_thru[13:0] to the fifo and begin to process data.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 289 document no.: pmc-2001304, issue 7 register 0x3280h:pl4idu configuration bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r/w reserved 0:high bit 8 r/w reserved 0:high bit 7 r/w reserved 0:high bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w synch_on_train 1 bit 1 r/w en_ports 0 bit 0 r/w en_dfwd 0 en_dfwd enable data forward. this bit is used to allow pl4 data words to be forwarded from the pl4idu. when ?1?, data will be forwarded. when ?0?, data will not be forwarded. the assertion and deassertion can result in partial pack ets. port statistics are incremented only if en_dfwd is a ?1?. en_ports enable port state machine. this bit is used to allow pl4 data words to be forwarded from the pl4idu. when ?1?, data will be forwarded. when ?0?, data will not be forwarded. the assertion and deassertion of this signal will not resu lt in partial packets. port statistics are incremented only if en_ports is a ?1?. synch_on_train should be set to 1.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 290 document no.: pmc-2001304, issue 7 register 0x3281h:pl4idu status bit type function default bit 15 reserved x:high bit 14 r reserved x:high bit 13 r reserved x:high bit 12 r reserved x:high bit 11 r reserved 0 bit 10 r reserved 0 bit 9 r reserved 0 bit 8 r reserved 0 bit 7 r unused x:high bit 6 r reserved bit 5 r run_orange bit 4 r run_yellow 0 bit 3 r run_green 0 bit 2 r pl4idu_disable 1 bit 1 r int 0 bit 0 r reserved 0 pl4idu_disable this is a registered value of the link state pl4idu_disable. this bit is provided for diagnostic purposes only. run_green this is a registered value of the link state run_green. this bit is provided for diagnostic purposes only. run_yellow this is a registered value of the link state run_yellow. this bit is provided for diagnostic purposes only. run_orange this is a registered value of the link state run_orange. this bit is provided for diagnostic purposes only.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 291 document no.: pmc-2001304, issue 7 register 0x3282h:pl4idu interrupt mask bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r/w reserved 0:high bit 7 r/w reserved 0:high bit 6 r/w reserved 0:high bit 5 r/w reserved 0:high bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w dip4e 0 bit 0 r/w ind_valide 0 ind_valide the ind_valide bit enables the generation of an interrupt due to the primary input signal ind_valid transitioning from a ?1? to a ?0?. dip4e the dip4e bit enables the generation of an in terrupt due to a dip4 check error on a pl4 control word.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 292 document no.: pmc-2001304, issue 7 register 0x3283h:pl4idu interrupt bit type function default bit 15 r unused x:high bit 14 r unused x:high bit 13 r unused x:high bit 12 r unused x:high bit 11 r unused x:high bit 10 r unused x:high bit 9 r unused x:high bit 8 r reserved 0:high bit 7 r reserved 0:high bit 6 r reserved 0:high bit 5 r reserved 0:high bit 4 r reserved bit 3 r reserved 0 bit 2 r reserved 0 bit 1 r dip4i 0 bit 0 r ind_validi 0 ind_validi the ind_validi bit will be set when the primary input signal ind_valid transitions from a ?1? to a ?0. if ind_valide is ?1? in the pl4idu interrupt mask register, an interrupt will also be ge nerated (int output asserted). dip4i the dip4i bit will be set when there is a dip4 check error. the dip4 checking is only done if the primary input signal ind_valid is asserted on the pl4 input interface. if dip4e is ?1? in the pl4idu interrupt mask register, an interrupt will also be generated (int output asserted).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 293 document no.: pmc-2001304, issue 7 12 test features description the following section will describe the test features implemented in the pm3392. 12.1 high impedance state for io test features to facilitate board testing include being able to place all output pins, including analog, in a high-impedance state. to achieve a high impedance state for the digital outputs the following steps can be taken: assert csb, rstb, and trstb to ?0? de-assert trstb to ?1? after 200ns write 0x0010h to register 0x4000h the combination of bit 4 of register 0x4000h and rstb low, sets the digital output to a hiz state. trstb is an asynchronous reset to regist er 0x4000h, therefore must be deasserted before the register write. another way to set digital outputs to high-imped ance is to simultaneously assert (low) the csb, rdb and wrb inputs. all digital output pins and the data bus (d[15:0]) will be held in a high- impedance state. this test feature may be used for board testing. to set the analog output pins to high impedance, the following steps can be taken: assert csb, rstb, and trstb to ?0? de-assert rstb and trstb to ?1? after 200ns write 0x2000h to register 0x2305h 12.2 test registers
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 294 document no.: pmc-2001304, issue 7 pm3392 test register 0 bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r unused 0 bit 6 r unused 0 bit 5 r unused 0 bit 4 r/w pmctstb 0 bit 3 r/w reserved 0 bit 2 r unused 0 bit 1 r/w reserved 0 bit 0 r/w hizio 0 hizio hizio works in conjunction with wrb, cs b, and rdb. when these signals are low together and hizio is written to ?1?, the digita l pins are set to a high impedance state. this does not effect the analog pins. pmctstb pmctstb is used for placing the device in test mode to be used for production testing.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 295 document no.: pmc-2001304, issue 7 pm3392 test register 4 bit type function default bit 15 r unused 0 bit 14 r unused 0 bit 13 r unused 0 bit 12 r unused 0 bit 11 r unused 0 bit 10 r unused 0 bit 9 r unused 0 bit 8 r unused 0 bit 7 r unused 0 bit 6 r unused 0 bit 5 r/w vclk6 0 bit 4 r/w vclk5 0 bit 3 r/w vclk4 0 bit 2 r/w vclk3 0 bit 1 r/w vclk2 0 bit 0 r/w vclk1 0 vclk1 ? vclk6 vlck is used as test clock inputs to help with production test vectors. 12.3 jtag test port the s/uni-1x10ge(pm3392) jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to section 13. table 17 instruction register (length - 3 bits) instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode ident ification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 296 document no.: pmc-2001304, issue 7 table 18 identification register length 32 bits version number 3h part number 3392h manufacturer's identif ication code 0cdh device identification 333920cdh table 19 boundary scan register name register bit cell type device id rclk 171 in_cell - rdat[1] 170 out_cell - rdat[0] 169 out_cell - rdat[3] 168 out_cell - rdat[2] 167 out_cell - rdat[5] 166 out_cell - rdat[4] 165 out_cell - rdat[7] 164 out_cell - rdat[6] 163 out_cell - rctl 162 out_cell - rdat[8] 161 out_cell - rdat[9] 160 out_cell - rdclk 159 out_cell - rdat[11] 158 out_cell - rdat[10] 157 out_cell - rdat[13] 156 out_cell - rdat[12] 155 out_cell - rdat[15] 154 out_cell - rdat[14] 153 out_cell - refsel[0] 152 in_cell - refsel[1] 151 in_cell - pause 150 in_cell - rsclk 149 in_cell - rstat[1] 148 in_cell - rstat[0] 147 in_cell - txdata4[3] 146 out_cell - txdata4[1] 145 out_cell - txdata4[2] 144 out_cell - txdata4[0] 143 out_cell - txclk4 142 out_cell - txclk4_src 141 in_cell - txdata3[3] 140 out_cell -
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 297 document no.: pmc-2001304, issue 7 name register bit cell type device id txdata3[1] 139 out_cell - txdata3[2] 138 out_cell - txdata3[0] 137 out_cell - txclk3 136 out_cell - txclk3_src 135 in_cell - txclk2 134 out_cell - txclk2_src 133 in_cell - txdata2[3] 132 out_cell - txdata2[1] 131 out_cell - txdata2[2] 130 out_cell - txdata2[0] 129 out_cell - txclk1 128 out_cell - txclk1_src 127 in_cell - txdata1[3] 126 out_cell - txdata1[1] 125 out_cell - txdata1[2] 124 out_cell - txdata1[0] 123 out_cell - rxdata4[3] 122 in_cell - rxdata4[1] 121 in_cell - rxdata4[2] 120 in_cell - rxdata4[0] 119 in_cell - rxdata3[3] 118 in_cell - rxclk4 117 in_cell - rxdata3[2] 116 in_cell - rxdata3[0] 115 in_cell - rxdata3[1] 114 in_cell - rxclk3 113 in_cell - rxdata2[3] 112 in_cell - rxclk2 111 in_cell - rxdata2[2] 110 in_cell - rxdata2[0] 109 in_cell - rxdata2[1] 108 in_cell - rxclk1 107 in_cell - rxdata1[3] 106 in_cell - rxdata1[1] 105 in_cell - rxdata1[2] 104 in_cell - rxdata1[0] 103 in_cell - dtrb 102 in_cell - oeb_tsclk 101 out_cell - tsclk 100 out_cell -
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 298 document no.: pmc-2001304, issue 7 name register bit cell type device id oeb_tstat[1] 99 out_cell - tstat[1] 98 out_cell - oeb_tstat[0] 97 out_cell - tstat[0] 96 out_cell - oeb_intb 95 out_cell - intb 94 out_cell - wrb 93 in_cell - rstb 92 in_cell - csb 91 in_cell - rdb 90 in_cell - a[0] 89 in_cell - a[1] 88 in_cell - a[3] 87 in_cell - a[9] 86 in_cell - a[13] 85 in_cell - a[2] 84 in_cell - a[5] 83 in_cell - a[4] 82 in_cell - a[7] 81 in_cell - a[14] 80 in_cell - oeb_d[1] 79 out_cell - d[1] 78 io_cell - a[6] 77 in_cell - a[10] 76 in_cell - a[11] 75 in_cell - oeb_d[0] 74 out_cell - d[0] 73 io_cell - oeb_d[2] 72 out_cell - d[2] 71 io_cell - oeb_d[5] 70 out_cell - d[5] 69 io_cell - a[8] 68 in_cell - a[12] 67 in_cell - ale 66 in_cell - oeb_d[3] 65 out_cell - d[3] 64 io_cell - oeb_d[6] 63 out_cell - d[6] 62 io_cell - oeb_d[9] 61 out_cell - d[9] 60 io_cell -
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 299 document no.: pmc-2001304, issue 7 name register bit cell type device id oeb_d[4] 59 out_cell - d[4] 58 io_cell - oeb_d[7] 57 out_cell - d[7] 56 io_cell - oeb_d[10] 55 out_cell - d[10] 54 io_cell - oeb_d[13] 53 out_cell - d[13] 52 io_cell - oeb_d[15] 51 out_cell - d[15] 50 io_cell - oeb_d[11] 49 out_cell - d[11] 48 io_cell - oeb_d[8] 47 out_cell - d[8] 46 io_cell - oeb_mdio 45 out_cell - mdio 44 io_cell - oeb_mdc 43 out_cell - mdc 42 out_cell - vclk2 41 in_cell - vclk1 40 in_cell - oeb_d[12] 39 out_cell - d[12] 38 io_cell - vclk3 37 in_cell - vclk4 36 in_cell - vclk5 35 in_cell - vclk6 34 in_cell - vclk_forceb 33 in_cell - oeb_rx_los 32 out_cell - rx_los 31 out_cell - oeb_d[14] 30 out_cell - d[14] 29 io_cell - oeb_paused 28 out_cell - paused 27 out_cell - phase_err 26 in_cell - oeb_phase_init 25 out_cell - phase_init 24 out_cell - sync_err 23 in_cell - oeb_rx_sysclk2 22 out_cell - rx_sysclk2 21 out_cell - oeb_tx_sysclk2 20 out_cell -
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 300 document no.: pmc-2001304, issue 7 name register bit cell type device id tx_sysclk2 19 out_cell - cpref_clk 18 in_cell - tdat[0] 17 in_cell - tdat[2] 16 in_cell - tdat[4] 15 in_cell - tdat[6] 14 in_cell - tdat[8] 13 in_cell - tdat[9] 12 in_cell - tdat[11] 11 in_cell - tdat[13] 10 in_cell - tdat[15] 9 in_cell - tdat[1] 8 in_cell - tdat[3] 7 in_cell - tdat[5] 6 in_cell - tdat[7] 5 in_cell - tdclk 4 in_cell - tdat[10] 3 in_cell - tdat[12] 2 in_cell - tdat[14] 1 in_cell - tctl 0 in_cell - note 1: when set high, intb will be set to high impedance. note 2: each output cell has its own output enable (oeb_*), except for the differential outputs. note 3: tctl is the first bit in the boundary scan chain, and rclk is the first bit out of the boundary scan chain. note 4: it is assumed that the differential i/o will drive or will be driven differentially. a logic 1 being driven on a differential output via the jt ag scan chain will cause a logic 1 to be driven onto ?positive? or ?_p? pin, and a logic 0 to be driven onto the ?negative? or ?_n? pin. a similar convention is true for differential inputs. boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table located above.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 301 document no.: pmc-2001304, issue 7 figure 13 input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 figure 14 output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 302 document no.: pmc-2001304, issue 7 figure 15 bi-directional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 16 layout of output enable and bi-directional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 303 document no.: pmc-2001304, issue 7 13 operation 13.1 power sequencing the pm3392 uses five separate power sources: vddo, vddi, avdhvref, pl4_avdh, and pl4_avdl. the pm3392 specifies the ground pins vss. the analog high power, pl4_avdh, must be conn ected to a properly de-coupled +3.3v supply. the analog high power, avdhvref, must be connected to a properly de-coupled +3.3v supply. the analog low power,pl4_ avdl, must be connected to a properly de-coupled +1.8v supply. the digital switching power pins, vddo, must be connected to a properly de-coupled +3.3v supply. the digital core power, vddi, must be connected to a properly de-coupled +1.8v supply. the digital and analog power pins that are of the same supply voltage can be sourced from the same physical power supply source. the ground pins can be connected to a common uninterrupted physical ground plane. the digital core and switching power pins, vddo and vddi, are to be de-coupled to the vss ground. each analog power pin is to be i ndependently de-coupled to the ground plane. the power-on sequence is as follows: ? vddo must come up before or simultaneously with pl4_avdh ? avdhvref and pl4_avdh must come up together and before or simultaneously with pl4_avdl ? vddo must come up before or simultaneously with vddi 13.2 device reset the reset pin of the pm3392 device (rstb ? active low) should be asserted for at least 1 ms to initiate a complete initialization, or re-initializa tion, of the device. while rstb is held low (logic 0) both the digital and the analog portions of the chip are being reset. before the de- assertion of rstb, it is required that all external clocks and refsel be stable for a minimum of 1ms. after de-assertion of the rstb pin the device will continue to hold its internal digital reset asserted until an internal timer expires after 10 to 14 ms.. this will allow the analog clock synthesizer (csu) for the high-speed device interf ace (the pl4 interface) to stabilize to the selected reference frequency before allowing the digital portions of the device to operate. the line side or xsbi interface recovers internal clocks by dividing down the supplied reference clocks. the divided clocks are stable with in a 200ns. to override the internal initialization sequencing and timer, dtrb can be toggled high. th is is only used for chip testing and debug. it is not recommended that dtrb be toggled by the user. this pin should be tied low at the board level.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 304 document no.: pmc-2001304, issue 7 when the rstb pins is de-asserted (logic 1), th e device reset can be controlled by writing to the configuration and reset control register. system status of analog training and progress can be viewed via the top level pm3392 device status register. the system programmer may also elect to reset the pm3392 via software commands. this is accomplished by writing to the pm3392 device configuration and reset control register. the programmer is to write the pl4_aresetb, xsbi aresetb and dresetb bits to a logic 0. this asserts a full device reset. the programmer must pause no less than 1ms (there is no upper limit) then de-assert by writing a logic 1 to pl4_aresetb and xsbi_aresetb. the programmer is to wait no less than 10ms (the re is no upper limit) then de-assert dresetb by writing a logic 1 to the device configuration and reset control register dresetb bit. as with assertion of the rstb pin the programme r must also insure that the refsel[1:0] pins are in a stable state and that all clocks for th e device are present for a minimum of 1ms prior to initiating a software reset sequence. note that th e internal 10ms digital reset delay timer is only initiated after an appropriate rstb pin reset sequence. asserting software reset via aresetb or dresetb will not properly sequence the delay timer. it is not recommended that software attempt a full device reset. however, a soft reset may be accomplished by de-asserting dresetb then re-asserting dresetb. this will reset all internal digital logic without effecting the clocks. block configuration after the device reset and 10ms wait time for cl ocks to become stable, it is recommended to configure and enable all blocks except the xsbi and pl4io. once all other blocks are configured and enabled, then the xsbi and the pl4io blocks can be configured and enabled. this allows for a clean start-up of the line and system interfaces. 13.3 line-side lvds interface overview a generic lvds link is implemented accord ance with ieee 1596.3-1996. the transmitter drives a differential signal through a pair of 50 characteristic interconnects, such as board traces, back plane traces, or short lengths of cable. the receiver presents a 100 differential termination impedance to terminate the lines. in cluded in the standard is sufficient common- mode range for the receiver to accommodate as much as 925mv of common-mode ground difference. 13.4 pos-phy level 4 introduction the pm3392 device, one of pmc-sierra?s 10 gigabit physical layer devices, utilizes the industry standard pos-phy level 4 system in terface to provide a common interface across multiple devices supporting various protocols a nd rates with an aggregate throughput of 12.5gbit/s. the pos-phy level 4 system interface consists of a pair of 16 bit data paths and a pair of 2 bit fifo status paths. for a detailed description of this interface please refer to the pos-phy level 4 specification. both the transmit and recei ve data paths operate at the same frequency ( i.e. rdclk frequency = tdclk frequency).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 305 document no.: pmc-2001304, issue 7 the pos-phy level 4 interface fifo st atus paths typically operate at 1/8 th the data path-rate with lvcmos i/o. the transmit fifo status path can operate at any speed up to 1/8 th the data path rate. the receive fifo status path operates at 1/8 th the data path rate. the terms ?egress?, ?transmit?, ?ingress? and ?receive ? denote the system relative flow of status or data across the pos-phy level 4 interfaces wher eas the terms ?in?, ?input?, ?out? and ?output? denote the device relative flow of status or data across the device interfaces. figure 17 shows the relationships between de vices communicating via the pos-phy level 4 interface. on the pm3392, the transmit inte rface consists of tsclk / tstat outputs and tdclk / tctl / tdat inputs, and the receive interface consists of rsclk / rstat inputs and rdclk / rctl / rdat outputs. for link layer devices the transmit interface consists of tsclk / tstat inputs and tdclk / tctl / tdat outputs, and the receive interface consists of (optional) rsclk / rstat outputs and rdclk / rctl / rdat inputs. 13.4.1 external components required for pl4 bus interface on the pm3392 the analog power pins on the pm3392 device that are associated with the pl4 bus interface must be properly decoupled. please refer to pmc application note pmc-2010770 (power supply filtering recommendations for xe non devices) for additional details. figure 17 pos-phy level 4 interfaces transmit link layer device tsclk tstat[1:0] tdclk tdat[15:0] tctl receive link layer device rsclk rstat[1:0] rdclk rdat[15:0] rctl tsclk tstat[1:0] tdclk tdat[15:0] tctl rsclk rstat[1:0] rdclk rdat[15:0] rctl phy device
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 306 document no.: pmc-2001304, issue 7 13.5 pos-phy level 4 clocking 13.5.1 pos-phy level 4 clocking modes the pos-phy level 4 interface s upports two data path-clocking modes: a master and a slave mode. in master mode, the pmc-sierra physical layer device (phy) derives the pl4 clock from reference input (refclk) and provides cloc king to the customer asic. in slave mode, the phy derives the pl4 clock from the transmit data clock (tdclk) received from the customer asic. the choice between master and slave clocking modes depends on board design considerations and the jitter performance expected on the customer asic device. the pl4 interface needs to be frequency lock ed regardless of which mode is chosen. slave clocking mode when in slave clocking mode the pmc-sierra phy derives its data clocks from the transmit data clock (tdclk) received from the customer asic device. figure 18 shows a pmc-sierra phy device connected to a customer asic device in slave clocking mode. figure 18 pos-phy level 4 slave clocking mode pmc sierra pm3392 phy device customer asic device tdclk master clocking mode when in master clocking mode the pmc-sierra phy derives its data clocks directly from an external reference clock (refclk) and provides a frequency reference to the customer asic device via the receive data clock (rdclk). figure 19 shows a pmc-sierra phy device connected to a customer asic device in master clocking mode.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 307 document no.: pmc-2001304, issue 7 figure 19 pos-phy level 4 master clocking mode customer device pmc sierra pm3392 phy device rdclk pl4_rclk 13.5.2 pos-phy level 4 clock mode configuration this section describes how to configure the cloc king mode for the pos-phy level 4 interface. the choice of clocking mode is indicated to the pm3392 device by the refsel[0] input pin on the device as follows: 0 = slave mode (tdclk is the frequency reference) 1 = master mode (refclk is the frequency reference) in slave mode the availability of the transmit da ta clock (tdclk) is indicated to the pm3392 device by the refsel[1] input pin on the device as follows: 0 = tdclk is valid when the rstb pin is de-asserted (immediate mode) clock initialization proceeds automatically. 1 = tdclk is not valid when the rstb pin is de-asserted (deferred mode) software intervention is required to complete clock initialization. in master mode the frequency of the referen ce clock (refclk) is indicated to the pm3392 device by the refsel[1] input pin on the device as follows: 0 = ? the data rate (311 to 350 mhz) 1 = ? the data rate (155.5 to 175 mhz) in master mode the refclk must be available when the rstb pin is de-asserted ( i.e. there is no deferred master mode). the refsel settings must not change after the rstb pin is de-asserted. 13.5.3 pl4 bus clock frequency selection for non-blocking operation the required minimum pl4 bus reference clock required to support non-blocking operation of the pm3392 (that is, to support continuous line-ra te ethernet frame data transfer in both the ingress and egress directions) is a function of numerous factors including the following:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 308 document no.: pmc-2001304, issue 7 ? the maximum size of ethernet frames in the application. ? the selection of the pl4 maximum burst length (for the pm3392, this is configurable in pl4mos max_transfer register) ? the minimum sop-to-sop spacing rule (configurable in the pl4odp configuration register). ? the pl4 training sequence frequency (configurable in the pl4odp max_t register the following table lists the minimum and maxi mum supported pl4 bus data transfer rates to support non-blocking operation. it is recommende d that the pm3392 be operated with the pl4 bus transferring data at 700 mega-cycles per second. table 20 pl4 bus data transfer rate for non-blocking operation maximum ethernet frame size (in bytes) minimum pl4 bus data transfer rate (mcps) 1518 (standard 802.3) 660 9600 (jumbo) 680 in the table above, the maximum ethernet frame size is for an untagged frame; a tagged frame will have a frame size 4 octets larger and is already taken into consideration. the max_transfer size programmed is assumed to be 128 bytes or greater. the max_t value is assumed to be programmed to at least 64 for non-blocking operation. pl4 data alignment modes (dynamic versus static) the egress data path of the pm3392 (tctl+/- and tdat[15:0]+/- pins) only supports the pl4 bus specification dynamic alignment mode. this requires that the peer pl4 device must send the pl4 training sequence at a certain minimu m rate. the minimum rate should be 4000 to 10000 pl4 bus clock cycles or 5.7us to 14.3us. it is also required that the peer pl4 device comply to the dynamic mode jitter specifications th at will also be referenced in the application note. the ingress data path of the pm3392 (rctl +/- and rdat[15:0]+/-) support both pl4 bus specification static and dynamic alignment m odes. please refer to pmc-2010198 ?pmc pl4 compliance statement? for a detailed application note . in static mode, training is disabled. also, in static alignment mode, careful attention mu st be paid to skew and jitter specification as outlined by the pl4 bus specification. 13.6 pos-phy level 4 initialization initialization of pmc-sierra?s pos-phy level 4 interface proceeds in several phases: 1. device reset (previously discussed) 2. clock acquisition 3. training
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 309 document no.: pmc-2001304, issue 7 4. configuration 5. enabling these phases represent the conceptual initializati on sequence. depending on the configured mode of operation there may be some overlap between phases. 13.6.1 clock acquisition clock acquisition begins during device reset with the de-assertion of the rstb pin. in immediate (master or slave) mode the selected reference clock (refclk or tdclk) should be valid at this point, and the csu will begin training to the supplied reference frequency. in deferred (slave) mode the transmit data cl ock (tdclk) input should be active but may not be operating at the correct frequency, e.g. because it is being driven from a csu which is still in frequency acquisition. in this case the training of the slave csu should track the training of the master csu with a moderate amount of time lag. completion of clock acquisition is determined by monitoring the frequency of the csu relative to the transmit data clock (tdclk) in both slave and master modes, and relative to the reference clock (refclk) in master mode only. in immediate (master or slave) mode the frequency lock detection functions are enable d immediately upon de-assertion of the device internal digital reset. at this point the csu should be properly trained to the selected reference frequency. the frequency lock detection functio ns should indicate reference in-lock within 500ms after the device internal digital reset is de-asserted. in deferred (slave) mode the output of the lock detect function must be ignored until the master device is driving a valid frequency reference (tdc lk) into the slave device, and the slave csu has had time to acquire frequency lock. this is accomplished by automatically setting two configuration flags (train_dis and odat_dis) at reset time when refsel[1:0] = 10, and delaying the training phase until software clears these flags, as described below. 13.6.2 training both the transmit data path (tctl / tdat) and the receive data path (rctl / rdat) are de- skewed during this phase. during training the ou tput end of the data path continuously sends the training pattern defined in the pos-phy leve l 4 standard (10 training control words / 10 training data words) to the input end. training proceeds somewhat independently in each direction. transmit data path training begins when the train_dis flag is cleared (by the device in immediate mode or by software in deferred mode) and the frequency lock detect function indicates that the csu is locked to the transmit data clock (tdclk), and in master mode only to the reference clock (refclk). during training the input data de-skew function a ligns the 17 parallel bit lanes of the transmit data interface to each other. the transmit da ta alignment function should indicate data in-lock within 6 s after transmit data path training begi ns when a valid training pattern is present at the transmit data interface (tctl / tdat). transmit da ta path training continues until the transmit data path is enabled, as described below.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 310 document no.: pmc-2001304, issue 7 receive data path training begins when the odat_dis flag is cleared (by the device in immediate mode or by software in deferred mode) and the frequency lock detect function indicates that the csu is locked to the select ed frequency reference (tdclk or refclk). during training the device continuously generat es the training pattern at the receive data interface (rctl / rdat) to allow the input end of the interface in the peer device to properly de-skew. receive data path training continues until the receive data path is enabled, as described below. 13.6.3 configuration the operation of pmc-sierra?s pos-phy level 4 interface requires several configuration parameters, including: 1. highest channel number used by the device (calendar_len) 2. transmit and receive fifo allocations and thresholds for each channel. 3. receive data scheduling parameters (max_burst1, max_burst2, max_transfer) 4. receive training scheduling parameters (data_max_t, alpha) 5. optional disabling of receive fifo status channel (no_status flag) it is recommended that parameters be confi gured in the order shown to avoid anomalous behavior. rules for setting the pl4 bus configuratio n parameters is described in a later section. 13.6.4 enabling enabling proceeds somewhat independently in each direction. after configuring all transmit interface parameters software must clear the os tat_dis flag. (as described in the training phase, the train_dis flag must also have been cl eared automatically or by software.) normal operation of the transmit fifo status and data interfaces commences when the ostat_dis flag is cleared and the transmit data ali gnment function indicates data in-lock. after configuring all receive interface parameters software must either set the no_status flag or clear the istat_dis flag. (as described in the training phase, the odat_dis flag must also have been cleared automatically or by so ftware.) normal operation of the receive fifo status interface commences when the istat_di s flag is cleared and the receive status alignment function indicates status in-lock. normal operation of the receive data interface commences when the no_status flag is set or the receive status alignment function indicates status in-lock. 13.6.5 pl4 bus configuration parameters the pl4 bus specification specifies a number of startup parameters that are configurable on a per-interface basis. all of the pl4 bus configuration parameters can be accessed via the microprocessor interface of the pm3392 device.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 311 document no.: pmc-2001304, issue 7 pl4 bus calendar_len the pl4 bus calendar_len parameter is repres ented by the top_chan[3:0] field of the pm3392 configuration and reset control register. the top_chan[3:0] is read only and set to 0. since the pm3392 device has only 1 internal pipe, calendar_len will always be 1. pl4 bus maxburst1 and maxburst2 for receive the pl4 bus maxburst1 parameter is held in the pl4mos maxburst1 register. on the pm3392 device pl4mos maxburst1 can take the value 8 to 4095 and represents a credit amount in blocks of 16 bytes. likewise, the pl4 bus maxburst2 parameter is held in the pl4mos maxburst2 register and can take the value 8 to 4095. it also repr esents a credit amount in blocks of 16 bytes. as per the pl4 bus specification, maxburst1 is to be programmed to be either higher than or equal to the value than maxburst2. on the pm3392 device there is no hardware bounds checking to ensure that this configuration requirement is met. the selection of maxburst1 and maxburst2 in a syst em application is related to the size of the receive buffering. a more detailed descrip tion can be found in the pmc-2010502 pos-phy level 4 frequently asked questions (pl4 faq). pl4 bus maximum burst length (max_transfer) max_transfer determines the maximum length of a pl4 data burst. the maximum databurst length parameter for output data (pm 3392 device rdat[15:0] and rctl) is held in the pl4mos transfer size register as max_transfer[7:0]. max_transfer defines the maximum size in a pl4 databurst in terms of 16-byte data blocks for the single pipe. the register is implemented so that the low two bits are read-only and hardwired to 2?b00, thereby constraining the configurable size to be modulo 4 (or at a 64-byte boundary). for example, a max_transfer value of 8 limits the pl4 databurst to transfers of at most 128 bytes or, equivalently, 64 pl4 bus cycles. the maximum burst length parameter for incomi ng data (device pins tdat[15:0] and tctl) is not held on the pm3392 and there is no require ment that the value of the parameter in the ingress and egress directions be the same. th e maximum burst length parameter for incoming data can range from 32 to 1024 bytes, in increments of 32 bytes. pl4 fifo threshold issues appendix c of pmc-991635 discusses the fifo status bandwidth requirements and fifo threshold issues. further details are provided below as they apply to the pm3392 device.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 312 document no.: pmc-2001304, issue 7 the thresholds for starving and hungry in the peer pl4 device are set such that the peer fifo can accept at least maxburst1 and maxburst2 (16-byte) blocks respectively, plus an additional amount to account for feedback-response delay. in order to guard against potential buffer underflow (which could affect total recei ve throughput if the sink device is unable to drain its fifo at a rate greater than the line rate ), the lowest threshold must be set high enough to allow the other end to respond to transitions to the state of lowest fifo occupancy in a reasonable length of time (to the order of the st atus update interval, plus scheduler response time). maxburst2 and maxburst1 (if applicable ) must be provisioned to allow adequate utilization of transfer bandwidth between status updates for the given port. figure 20 shows one possible way for relating wo rst case fifo thresholds to maxburst1 and maxburst2 as well as the response latency. for receive the receive and transmit directions, lmax and epsilon can take different value. lmax corresponds to the worst-case response time, starting from the delay in receiving a status update over the fifo status channel, and observing the reaction to that update on the corresponding data path. the margin, epsilon, is an implementation-specific quantity that accounts for differences between the calculated/designed and actual lmax. figure 20 sample fifo thresholds (ae = almost empty waterline, af = almost full waterline) a e a f starving hungry satisfied (empty) (full) max + l maxburst1 max + + l maxburst2 max + + l the contribution to lmax by the pm3392 device in the receive direction (data flow on rdat pins) is approximately 1200 bytes for a max_transfer size of 128 bytes. increasing max_transfer will result in an increase in lm ax and can be approximated as follows: lmax ~ 1200 + 3*(max_transfer ?128) bytes; the contribution to lmax by the pm3392 device in the transmit direction (data flow on tdat pins) is approximately 800 bytes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 313 document no.: pmc-2001304, issue 7 pl4 bus sop-to-sop spacing rule the pl4 bus parameter that specifies the start-o f-packet to start-of-packet spacing rule for output data is held in the pl4odp configuration register sop_rule[1:0] field. the pm3392 supports a configurable minimum sop- to-sop spacing of 2 and 8 pl4 bus cycles on the output data (pm3392 device rdat[15:0] and rctl). for pl4 bus input data (tdat[15:0] and tctl) the pm3392 device requires a minimum sop- to-sop spacing rule of 4. if the spacing is less than 4, this can cause the fifo to fill erratically. if the condition persist, a fifo overflow could result. pl4 bus maxburst1 and maxburst2 for transmit the maxburst1 and maxburst2 parameters for i nput data are not held on the pm3392 device. these parameters are required to be implemente d either as a programmable or fixed value on the peer pl4 device that sources data on the pl4 bus tdat[15:0] pins. the value of maxburst1 and maxburst2 for input da ta and output data do not have to be equal. pl4 bus calendar_m the pl4 bus calendar_m parameter is represented by the in_mul[7:0] and out_mul[7:0] fields of the pl4io calendar repetitions register. the number of repetitions of the input fifo status channels (impressed on pm3392 device input pins rstat[1:0]) within a complete stat us calendar sequence is controlled by in_mul. the pl4 input status parameter calendar_m = in _mul + 1. the total length of the input status calendar sequence = calendar_len x calendar_m. in_mul must be changed while the input status interface is disabled in th e pl4io configuration register. the result of changing in_mul while the status interface is en abled is unspecified. in_mul can take the value 1 to 255 if the input fifo status channel is enabled. as per the pl4 bus specification, the input fifo status channel is optional, but will only reflect a single channel status on the pm3392. the number of repetitions of the output fifo st atus channels (impressed on the pm3392 device output pins tstat[1:0]) within a complete status calendar sequence is controlled by out_mul. the pl4 output status parameter calendar_m = out_mul + 1. the total length of the output status calendar sequence = calendar_len x calendar_m. out_mul must be changed while the output status interface is disabled in the pl4io configuration register. the result of changing out_mul while the status interface is enabled is unspecified. out_mul can take the value 1 to 255. pl4 bus max_calendar_len the maximum supported value for max_ca lendar_len follows from the maximum supported value of both ca lendar_len and calendar_m: max_calendar_len = max(calendar_len) x max(calendar_m); = 10 x 256 = 2560;
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 314 document no.: pmc-2001304, issue 7 pl4 bus fifo_max_t the pl4 bus parameter fifo_max_t is the product of calendar_len and calendar_m. pl4 bus data_max_t as per the pl4 bus specification, ?for the da ta path de-skew procedure, data_max_t is configured only on the sending side of the data paths on the transmit and receive interfaces. data_max_t need not be identical over both interfaces.? the pl4 bus data_max_t parameter for the output data path is held in the pl4odp max_t register. max_t[11:0] defines the bounded time interval over which the pl4 training sequence is to be sent. the value of max_t is in terms of 1024 pl4 bus cycles. a value of 0 in the max_t register disables the sending of the training sequence (no training patterns sent). although any integer value of max_t can be programmed, in order to maintain the non- blocking operation of the pm3392 a maximum of 0.1% of the pl4 bus cycles should contain a forced training data pattern or training control pa ttern. this limits the lowest practical value for which max_t can be programmed (if non-zero) to 16; for a value of 1, this would imply that at a minimum the 20 cycle training pattern would be sent every 1000 - 4000 pl4 bus cycles. pl4 bus data training sequence repetitions ( ) the pl4 bus parameter that specifies the number of back-to-back training patterns that define a training sequence for outgoing data (pm3392 de vice rdat[15:0] and rctl) is held in the pl4odp configuration register repeat_t[3:0] field. numerically: = repeat_t + 1; where can take the value of 1 to 16. for incoming data (pm3392 device tdat[15:0] and tctl) the value of is not held. for correct operation of the pm3392 input deskew logic, can take on any value greater than or equal to 1. operation with pl4 bus receive fifo status unimplemented the pm3392 device supports the pl4 bus specifi cation requirement that the receive fifo status is optional. in the event that the p eer pl4 sink device does not implement the receive fifo status, the no_status bit in the pl4mos configuration register is to be written to a logic 1 prior to enabling the pl4mos (which is done by writing pl4mos_en to a logic 1). in this case, each the pm3392 is assigned an infin ite credit. the scheduler on the pl4mos works as previously described but with an implied fifo status of sta (starving). 13.7 pl4 bus operation this section provides some additional operati onal details of the pl4 bus interface on the pm3392 device.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 315 document no.: pmc-2001304, issue 7 13.7.1 pl4io initialization after power up the pl4io functional block on th e pm3392 device must be properly initialized to ensure normal operation. the normal initialization sequence is: ? the device is reset, either through assertion of the rstb pin or by a software reset via the areset and dreset register bits, as previously described (see device reset). ? the pl4io control logic trains the on-chip pl4 csu to the selected reference clock. the reference clock select (refsel[1:0]) selects the source (pl4_rclk in master mode or tdclk in slave mode) and frequency of the refe rence clock used to generate the internal clocks for the entire pl4io subsystem. trai ning to the reference clock begins when the internal analog reset is deasserted and continu es until reference lock has been detected. the pl4io control logic continuously checks for reference lock while digital reset is deasserted, and generates an internal locked status for the csu when the synthesized csu clocks are locked to the selected referen ce frequency. the pl4io control logic also updates an internal locked status for the i nput data when the input data clock (tdclk) is locked to the synthesized csu clock frequency ? the pl4io control logic trains the on-chip dru to the input data stream from the peer pl4 device. training to the input data stream begins when digital reset is deasserted and continues until the input data stream has been locked. the pl4io control logic continuously checks for input data rate lock while digital reset is deasserted and the input data clock (tdclk) is locked to the synt hesized csu clock frequency, and updates the locked bit maintained for each in eac h, per-bit, internal input fifo. the locked bit for a given internal input fifo will be cleared at any time it is determined that there is an overflow or underflow on the fifo. ? the pl4io control logic automatically se quences the internal analog and digital components through the initialization process without system intervention. the external logic is only required to provide the de fined sequencing of the reset signals. software can track the progress of pl4io initialization by monitoring the pl4_out_rool and pl4_id_rool in the pm3392 device status register. software can periodically poll these registers or it can selectively arm an inte rrupt (rool_int) when their contents change: see pl4io lock detect change register. software can also override the initial configuration for link testing by writing a non-default configuration to the pl4io registers. 13.7.2 pl4io csu lock detect logic the pl4io lock detect logic controls and mon itors the csu abc. the csu is continuously trained to the selected reference clock (pl4_rclk or tdclk as determined by refsel[1:0]). after training is complete the lvds transmitter abcs may be enabled for normal data transmission.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 316 document no.: pmc-2001304, issue 7 the lock detect logic produces the output reference out of lock (pl4_out_rool) and input data reference out of lock (pl4_id_ rool) outputs, which are available via the pm3392 device status register. optional interrupts can be produced whenever pl4_out_rool or pl4_id_rool changes: see pl4io lock detect change register. the clock speed comparators continuously monito r the csu frequency, relative to the reference clock (pl4_rclk) and the input data clock (tdclk), to determine if the both the current device and the peer pl4 device have achieved frequency lock. this is achieved by counting clock edges in a fixed window and then compari ng this to the allowed value specified in the ref_limit field of the lock detect limits register. if the difference exceeds this value pl4_out_rool or pl4_id_rool will be asserted, causing the internal status out_dis to be asserted or ind_valid to be deasserted. assertion of out_dis internal to the pm3392 device will result in sending of the error sequence on the tstat[1:0] status bus and, on the egress datapath, the training pattern will be continuously generated. deassertion of ind_valid results in the pl4idu invalidating data transferred from the pl4io and aborting all active channels (that is, all partial packets that have not been terminated by an eop will internally be terminated with an eop_abor t status in the pl4idu and be transferred downstream to the eflx, which will result in the terminated ethernet frame being sent on the ethernet transmit media with an error indicati on). further packet reception by the pl4idu is held off until ind_valid becomes asserted. 13.7.3 pl4io input data reception the pl4io data input logic that processes the data received on the tdat[15:0]+/- and tctl+/- device pins produces the input data reference out of lock (pl4_id_rool) and input data out of lock (pl4_id_dool) outputs, which are available via the pm3392 device status register. optional interrupts can be produced whenever pl4_id_rool or pl4_id_dool changes value, under control of the pl4io lock detect status register. the pl4io data input logic performs the pl4 desk ew function. by use of individual receive fifos for each of the 16 data channels, data can be skewed relative to the clocks. this allows for both jitter on the pl4 data bus and quantization error in the on-chip dru. software can track the progress of the pl4io input data deskew operation by monitoring pl4_id_dool. software can also enable / disable the input data deskew operation by clearing / setting the train_dis bit in the pl4io configuration register. this bit should not be cleared in slave mode until the input data cl ock (tdclk device pin) is valid and stable. to ensure that the on-chip dru is synched to the incoming data stream, the pl4io data input logic waits for the number of transition events specified in the tran_limit bits in the pl4io lock detect limits register before transferring data to an internal receive fifo. after dru training is complete pl4_id_rool is de-asserted. pl4_id_rool will be asserted if it is determined that the internal per-bit receive fi fo has overrun or under -run (also referred to as input data slip).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 317 document no.: pmc-2001304, issue 7 after dru training is complete the training pattern logic is enabled. when the training pattern is concurrently detected in each of the 16 receive fifos the align_ready signal is asserted. this causes each of the fifos to initialize its read pointer, so the data will be read in phase from all channels. when the de-skew process is complete pl4_id_dool is de-asserted and ind_valid is asserted, enabling the input data path in the downstream pl4idu block. ? the following diagram provides an indication of the pl4io data in state machine. data encapsulated in pl4 data bursts transferred by the peer pl4 entity across the tdat[15:0] and tctl device pins will be transferred in the pm3392 from the pl4io to the downstream pl4idu block when the pl4io is in the ?s_align? state. figure 21 pl4io data in state diagram s_seek s_align s_hold s_check tcw = 1 and align_ready = 1 tcw = 1 and tpat = 1 tcw = 1 and tpat = 1 tcw = 1 and align_ready = 0 tcw = 1 and tpat = 0 tcw = 1 and tpat = 0 reset = 1 r e s e t = 1 tcw : training control word tpat: training pattern align_ready: and version of signal ready form 17 channels reset: input data clock out of lock or input data slip or reset = 1 13.7.4 pl4io tstat fifo status generation the pl4io status output logic internally accepts two bit status inputs (outs0, outs1), and encapsulated them into the two bit parallel fifo status output stream (device tstat[1:0] pins) and divides the pl4 subsystem input data clock (a divided-by-4 version of tdclk, hereafter referred to as inclk) by 2 to produce the output status clock (tsclk). all of the status processing logic uses inclk, which is common to the input data side pl4 subsystem.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 318 document no.: pmc-2001304, issue 7 the main status output state machine generat es the fifo status framing structure. when in_dis is asserted the state machine outputs contin uous ?11? framing words. this inhibits the input state machine in the peer device from sy nchronizing to the incoming framing structure in the peer device. the calendar state machine traverses the tdm status calendar and multiplexes the parallel channel status from the pl4 input fifo into the fifo status stream. 13.7.5 pl4io rstat fifo status reception the pl4io status input logic parses the two bit parallel fifo status input stream (rstat[1:0] device pins) and internally produces two bit status outputs (ins0, ins1). the status stream is resampled by a divide-by-four version of rdcl k (hereafter called outclk), which is always at least twice the speed of rsclk. all of th e status processing logic uses this outclk which is common to the output data side of th e pl4 subsystem internal to the pm3392. the status input logic produces the input stat us reference out of lock (pl4_is_rool) and input status data out of lock (pl4_is_dool) outputs, which are available via the pm3392 device status register. optional interrupts can be produced whenever pl4_is_rool or pl4_is_dool changes value: see pl4io lock detect status register. the clock speed comparator continuously monito rs the rsclk frequency, relative to the output data clock (outclk), to determine if the rs clk is running faster than ? the frequency of outclk. if the rsclk frequency exceeds this limit pl4_is_rool will be asserted, causing out_dis to be asserted. the main status input state machine synchronizes to the fifo status framing structure. if the state machine cannot synchronize to the incoming framing structure pl4_is_dool will be asserted, causing out_dis to be asserted. the calendar state machine traverses the tdm st atus calendar and demultiplexes the channel status stream for parallel presentation to the pl4 output data scheduler (pl4mos). monitoring of rstat fifo status upon deassertion of digital reset, the pl4io contro l logic continuously checks for the frequency of input status clock (rsclk). the sending side of the fifo status channel is initially in the disable state and sends the ?11? pattern repeatedly. when fifo status transmission is enabled, there is a transition to the sync stat e and the ?11? framing pattern is sent. fifo status words are then sent acco rding to the calendar sequence (of length top_chan[3:0] + 1), repeating the sequence followed by the dip-2 c ode. the repetition of the calendar sequence is determined by the out_mul[7:0] in the calendar repetitions register.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 319 document no.: pmc-2001304, issue 7 figure 22 pl4io fifo status state diagram s_dip2 s_sync s_disable chan(0) chan(1) chan(2) chan(top_chan) s_calendar iteration #1 iteration #2 iteration #calendar_m disable 11 11 11 dip2 outs(0) outs(1) outs(2) outs(top_chan) outs(0) outs(1) outs(2) outs(top_chan) outs(0) outs(1) outs(2) outs(top_chan) the input fifo status operation begins after di gital reset is de-asserted and the pl4_is_rool is logic 0 (indicating rsclk is in the required frequency range). the pl4io logic follows the status stream patt ern and determines if an error occurs in the incoming fifo status stream. the aligned bit in the pl4io input fifo mode register is set to logic ?1? after a complete status pattern from sync to dip-2 is detected successfully. an pl4_is_rool assertion (logic 1) clears the aligned bit and resets the pl4io data_in state machine.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 320 document no.: pmc-2001304, issue 7 figure 23 pl4io status in state diagram s_seek s_align s_hold s_check frm_frmb frm_frmb frm_frmb disable or error error disable d i s a b l e o r e r r o r frm_frmb: transition from sync to calendar error: calendar_dip2b or dip2_frmb or dip2b_frm disable: isclk out of lock or disable by configuration software can track the progress of pl4io input fifo status operation by monitoring the pl4_is_rool and pl4_is_dool in pm3392 device status register. software can periodically poll these registers or it can selectively arm interrupts (rool_int and dool_int of pl4io lock detect status register) when their contents change. software can also enable / disable the normal input fifo status operation by clearing / setting the no_istat and istat_dis in the pl4io configuration register. 13.7.6 pl4 ingress training pattern generation at device startup the output data path (pl4 rctl and rdat[15:0] pins) is disabled. during device initialization the pl4 output data state m achine begins to generate training patterns; however other state machines handle other parts of the pl4 initializations. when the lvds transmitters become active the output data state machine may be at any arbitrary point in the training pattern. therefore a customer asic device must be prepared for the initial training sequence to start on any arbitrary boundary within the training pattern.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 321 document no.: pmc-2001304, issue 7 during normal operation after initialization completes, the pl4 output data state machine generates ?opportunistic? training patterns whenever the data pipeline is empty. the generated training sequence begins with an idle control word, followed by 10 training control words and 10 training data words. the 20 word training pattern may be repeated an arbitrary number of times, depending on when data becomes available in the pipeline. therefore a customer asic device must be prepared for an arbitrary numbe r of repetitions of the training pattern without intervening idle control words. the pl4 output data state machine ensures that a training sequence of minimum length repeat_t (the pl4 parameter) is generated at least on ce in every (max_t + maxtransfer) cycles. 13.7.7 pl4idu error handling as stated previously, the pos-phy level 4 specification defines correct operation, but generally does not define error handling except where it affects interoperability between the peer devices. consequently different devices may handle the same error differently. the following section outlines error handling as done on the pl4idu interface that may affect higher-layer protocols in the event that errors are detected at the pl4 bus tdat[15:0], tctl, and tdclk interface. the pl4idu is designed so that all single cycle pl4 bus errors are non-catastrophic and recoverable. the basic classes of errors are as follows: 1. there is an error detected in the pl4 word parsing 2. there is a breakdown in the sop->data->eop protocol on the input data the pl4idu always re-synchronizes on the next valid eop when a sop->data->eop protocol error occurs. this behavior will cau se the next sop->data->eop packet to be aborted until there is a valid eop to re-synchronize to. behavior in the case that mac is configured to append framechecksequence on transmit and a detectable error occurs on the pl4 bus during the data transfer in order to guarantee that any corruption of data that may occur during pl4 bus databurst transfers is detected at the ethernet link partne r (data sink) with respect to the data as present internal to the data source (the pl4 egress source asic, see figure below) it is necessary that the mac must not be programmed to modify the frame contents. specifically, the paden bit must be logic 0 and the crcen bit must be logic 0. in this mode, any data corruption that may result during the transfer of data will be detectable at the data sink during the transfer of the ethernet physical packet: either the packet is marked as erred during the data transfer from the pm3392 device or the framechecksequence field of the physical packet will be erred.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 322 document no.: pmc-2001304, issue 7 pm3392 line i/f pl4 bus i/f pl4 egress source asic tdclk tctl tdat[15:0] egress traffic flow ------------------> xsbi_tx[15:0] +/- pl4 bus ethernet transmit link media ethernet link partner a corollorary to the above statem ent applies. specifically, if either the mac paden bit is set to logic 1 or the crcen bit is set to logic 1 it is possible that an ethernet frame is received at the ethernet link partner with a correct framec hecksequence but that the internal ethernet frame contents as represented at the data source device may have been modified. the error rate of this occurring is less than that of the data transfer error rate on the pl4 bus media itself assuming that the pl4 egress source asic is itself error-free. data integrity can be assured at the data sink device by doing a dditional verification of the received ethernet frame: these checks can include a length check and any higher-protocol layer crc checks. in summary, to guarantee the highest probability of end-to-end error detection at the lowest- possible level of the communications protocol stack then data transfer across each possible communications link (in this case the pl4 bus) mu st include an error protection code for each protocol layer. for the case of interfacing to the pm3392 device, this means that ethernet frame transfers across the pl4 bus will have a higher probability of being detected as erred if they include the framechecksequence field and the pm3392 device checks the fcs field during frame transmission. 13.8 xsbi wrapper line interface 13.8.1 initialization upon power up both analog reset (xsbi areset) and digital reset (dreset) are asserted simultaneously or analog reset followed by digital reset. analog reset initializes the analog circuits to a known state, whereas digital reset initialize all normal mode ecbi registers and xsbi_wrapper retime registers to their default value. 13.8.2 configuration the configuration register bit xsbi_en must be set to ?1? in order for the data to be forwarded to and from the pcs. by default the bit-swizzle is turned off and the oifs_en is set to ?1?. bit- swizzle defaults to the ethernet lan mode of operation. to program the configuration register xsbi_en must be disabled. no additional c onfiguration is required in normal operation.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 323 document no.: pmc-2001304, issue 7 13.8.3 prbs testing this is a diagnostic mode for testing the sipo/p iso (serial in parallel out/ parallel in serial out) analog blocks of the oifs abc. prbs generation prbs generation mode overwrites incoming data stream and provides prbs sequence to the 16 piso?s which in turn outputs the generated p rbs through the transmit side of the chip. to enable this mode the mpgm_gen_en bit in the configuration register must be set to ?1?. prbs monitor prbs monitor mode detects prbs sequence on the output of the 16 sipo?s and reports a lock condition. to enable prbs monitor mode the mpgm_mon_en bit in the configuration register must be set to ?1?. 13.8.4 interrupts reporting of xsbi_wrapper interrupt conditions are enabled or disabled by writing to the corresponding mask register. the interrupt pin is a logical or of all the enabled interrupts. please refer to the register description section for va rious interrupts and interrupt enables(mask registers). by default the interrupts are disabled. 13.9 loopback operation xsbi local loopback mode local loop-back (system side) ties the output of the pcs transmit 64b66b decoder block to the input of the pcs receive 64b66b encoder block. to enable this mode, set bit 5 (local_loopback_en) of register 0x0100 xsbi wrap per configuration register to ?1'. when the local_loopback_en bit is set to ?1? the output pins txdata[15:0] will output the value 0x00ff until local_loopback_en is set to ?0? which will resume normal operation. pl4 system-side (local) loopback the source of the 68-bit parallel data stream for the piso in the output interface of the pl4io logic can be configured to support system-side (local) loopback by setting the outsel[1:0] bits to 2?b11. in this loopback mode, the da ta stream impressed on the pl4 tdat[15:0]+/- and tctl+/- pins goes through a sipo and is writte n as a 68-bit parallel data stream comprising four pl4 bus words into an internal fifo. the s ource of the 68-bit parallel data stream used by the piso for impressing on the pl4 rdat[15:0]+/- and rctl+/- device pins is read from this internal fifo. the pl4 status bus may optionally be looped back by setting the stat_outsel bit to 1. in this mode the status calender impressed on the rstat[1:0] device input pins is looped directly back onto the tstat[1:0] output pins. if stat_outsel is set to 0 and outsel[1:0] is set to ?11?, the status that gets driven onto tstat[1:0] reflects the state of the device eflx. in this mode of operation, th e potential exists for the pl4 partner's receive buffer to be overflowed if cannot keep up with its (the partner's) transmitter.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 324 document no.: pmc-2001304, issue 7 note that in this loopback mode it is the act ual serial bit stream from the tdat[15:0]+/- and tctl+/- device pins that is being looped back. therefore it is not required that the injected data stream represent an ethernet frame.in this mode, tx frame data impressed on pl4 tdat gets forwarded to the mac in addition to the loo pback paths. as a consequence, test frames that a pl4 partner wishes to use to verify the opera tion of its pl4 interface get egressed to the pm3392's link partner and counted by the mstat bl ock as valid network traffic. if this is not desired, one may disable the pl4idu via the pl4idu configuration register en_ports and en_dfwd register bits before configuring th e pl4io into local loopback mode. the pl4idu must be re-enabled to allow line side eg ress if loopback is subsequently disabled. pl4 remote (line-side) loopback the insel bit of the pl4io configuration register selects the source of the 68 bit parallel data stream for the pl4idu. the default setting of insel, logic 0, selects the pl4 incoming dru input data stream from the sipo as the source of the pl4idu 68-bit data word, ind[67:0]. remote (that is, line-side) loopback of the pl4 internal datapath is accomplished by setting insel to logic 1: the source of the pl4idu 68-bit data word, is selected to be the pl4odp output data stream; this results in data being looped-back from the device rxdata[15:0]+/- input pins to the txdata[15:0]+/- output pins. note that in this loopback mode that the inj ected data stream represents an ethernet frame. if pl4io insel is logic 1 (remote loopb ack from pl4odp to pl4idu) and pl4io outsel[1:0] is b01 (normal operation) data w ill be impressed on the pl4 rdat[15:0], rctl pins. if the user would like to disable the transfer of data on the pl4 rdat[15:0],rctl interface pins then the following can be done: step 1: program pl4io outsel[1:0] to b00. this will result in the rdat[15:0],rctl pins being driven to a logic 0. step 2: pl4io insel can be programmed to logic 1 to configure the pl4 interface for remote loopback. when insel is set to 1 the pl4 interface must be in master mode and have a valid reference clock for the loopback operation to work properl y. the pl4io lock status logic continues to check the lock status on the device?s pl4 inte rface pins. this will not effect the remote loopback operation even if the pl4io reports is/id rool/dool out-of-lock, it means the pl4 partner is not configured or present. 13.10 controlling ethernet fram e reception and transmission the reception and transmission of ethernet frame s within the pm3392 can be halted or enabled under software control. the txen0 and rxen 0 bits within the transmit and receive macs (txxg and rxxg) configuration register enables and disables the transmit and receive data flows respectively. in addition, the fctx, fcrx and parf bits determine the response of the pm3392 to mac control frames.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 325 document no.: pmc-2001304, issue 7 13.10.1 enabling and disabling reception when the rxen0 bit is deasserted (logic 0), the channel will cease data reception of both mac data frames and mac control frames at the next frame boundary (that is, during the interframe gap). if the channel is in the middle of receiving a frame, the frame reception will complete. all further frames, both mac data frames and mac control frames, that ingress at the rxxg line side interface will be ignored. all frames th at have been received prior to halting and are buffered within either the rxxg receive fifo or the iflx fifo for this channel will continue to ingress. these frames will be transferred across the pm3392 device rdat[15:0] pins as per the pl4 bus protocol. by default the pm3392 co mes out of reset with the rxen0 bit logic 0 (i.e. reception disabled) it is possible to select whether a mac control frame is forwarded to the system side pl4 interface. the parf bit of the rxxg gmacc1 regi ster controls this feature. by default, mac control frames are not forwarded. the fcrx bit in the txxg configuration 1 register determines whether the mac control sublayer for this channel will respond to a r eceived mac pause control frame. if fcrx is a logic 1 and a mac pause control frame is recei ved, the pause timer counter will be loaded with the pause_time value of the received frame. if fcrx is a logic 0, the load of the pause timer counter is inhibited and the transmit of ma c data frames from this channel is not paused. 13.10.2 enabling and disabling mac transmission the ethernet mac transmit interface will be disabled if the txen0 bit of the txxg configuration 1 register is logic 0. txen0 is logic 0 when the pm3392 comes out of reset. to enable the mac interface to transmit eith er mac data or mac control frames, txen0 must be logic 1. the txen0 is used to enabled and disable the transmission of mac data frames and mac control frames. when the txen0 bit is set to logic 1, the t xxg will cease data transfer for the transmit or egress direction on the pm3392 device. if the t xxg is in the middle of sending a frame, that frame will be finished without error. the pm3392 will then cease to transmit further mac data frames. if the system-side source device continu es to transfer data to the pm3392 for this channel (over the pl4 tdat[15:0] pins), th e data will be buffered until all egress buffer resources have been used on the eflx fifo. th e egress buffer resource levels are reported to the system source device using the pl4 bus fifo status signals over the tstat[1:0] pins. 13.11 ten gigabit ethern et interframegap support the pm3392 operates on frames having a range of interframegap (ifg) at the ten gigabit ethernet mac interface. the receive ifg setti ng is fixed whereas the transmit ifg spacing is programmable.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 326 document no.: pmc-2001304, issue 7 13.11.1 ten gigabit ethernet receive ifg the pm3392 can receive frames continuously with an ifg of equal to or greater than 40 bit times or 5 bytes. the normal receive interval is specified as the time between the last octet of the framechecksequence on the previous frame and the sampling of the start of frame delimiter (sfd). note that the 9.6 ns minimum receive interval encompasses the time required for the interframe gap, preamble octets and start frame delimiter. 13.11.2 ten gigabit ethernet transmit ifg for transmit or egress traffic the pm3392 will insert a minimum ifg of 12 bytes or 9.6 ns by default. the transmit ifg can also be programmed to allow a minimum ifg or 5 bytes or 4 ns. the ipgt[5:0] field in the txxg configurati on 1 register defines the back-to-back ifg between frames and can be set to one of th e non-reserved values as per the table below. table 21 transmit interpacket gap encoding ipgt[5:0] ipg (in bytes) comment 05h 5 06h 6 07h 7 08h 8 09h 9 0ah 10 0bh 11 0ch 12 default value 10h 16 14h 20 18h 24 1ch 28 20h 32 24h 36 28h 40 2ch 44 30h 48 34h 52 38h 56 3ch 60 any other value -- reserved to ensure 32-bit alignment while transmitting back-to-back frames with minimum ifg, the txxg does the following:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 327 document no.: pmc-2001304, issue 7 ? for lan mode the 32bit_align bit in the txxg configuration 1 register needs to be set. this will cause the mac to then insert and delete gaps in the data stream to maintain 32bit alignment and to maintain, on average, the programmed ifg for all frames sizes. in all cases, back-to-back frames will be sent with a transmit interval from the last octet of the fcs of the previous frame to the first octet of data in the next mac frame of 160 bit-times (which is 96 + 64) if the ipgt encoding is 0x0c; in the case that the ipgt encoding is 0x0b, the transmit interval is 152 bit-times and so on as per the above table. 13.12 ten gigabit ethernet preamble support 13.12.1 transmit preamble on ethernet transmit frames, the txxg will alwa ys insert the 802.3ae specified preamble: the preamble is 7 bytes, aligned on 32-bit boundari es having the octet value 0x55 (serialized bit stream of 10101010 with serial transmission occurring from left to right). the 7-byte preamble is followed by a one-byte startofframedelimiter, sfd: having the octet value 0xd5 (serialized bit stream of 10101011 with serial transmission occurring from left to right). 13.12.2 receive preamble the txxg includes configurable options on how it will interpret the preamble and startofframe delimiter (sfd) at the reconc iliation sublayer. this is done through the rxxg - configuration 1 register: purep and longp. preamble checking of the content of the preamble field of the packet, ensuring a data pattern of 0x55, is done only if purep is a logic 1. if pure p is a logic 0, then the data pattern during the preamble is not checked. in either case, purep does not affect any length check on the preamble. the 802.3ae specification for full duplex operation does not require that purep be set to logic 1. note that the default mode of this register bit is logic 0 the ability of the mac receive process to ignore frames based on the length of the preamble is controlled by the longp register bit. if set to logic 1, the mac receive process will accept frames having preambles greater than 11 bytes in length. if longp is set to logic 0, packets with preambles greater than 12 bytes will be igno red. the 802.3ae specification for full duplex operation does not require that longp is ever set to logic 1. note that the default mode of this register bit is logic 0: by convention ethernet frames having preambles of greater than 11 bytes are ignored. the preamble and sfd are stripped on every recei ved frame, converting the physical packet to an ethernet frame. only the data octets from the internal reconciliation frame stream are transferred: internal reconciliation frame stream: ethernet frame as transferred on pl4 bus system interface:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 328 document no.: pmc-2001304, issue 7 13.13 ten gigabit ethernet m ac transmit padding and crc generation the txxg can pad a frame for transmission that is forwarded from the pl4 system interface and is greater-than-or-equal-to 14 bytes. th is is accomplished only if the paden and crcen bits are set in the txxg configuration 1 register. the frame is padded with data octets having the value 0x0 to 60 bytes if not tagged or 64 by tes if tagged; a 4 octet fcs is appended to the frame prior to transmit. the pm3392 can append a proper four-octet fcs to each and every frame prior to transmission if the crcen bit within the txxg configuration 1 register is set. as previously described, frames without an error indicator having a length of at least 9 bytes to 14 bytes and if the paden bit is set will be pa dded to 60 bytes and then a bad crc is appended to the frame and the error flag is also asserted to the pcs layer to guar antee that the frame is properly marked as bad. 14 bytes are required for the ethernet frame destination address (6 octets), source address (6 octets), and length/type field (2 octets). frames that are less than 9 bytes will be discar ded and an internal de bug counter will count the number of times a packet is discarded due to less than 9 bytes. table 22 pm3392 minimum transmit frame size padding frame length at internal transmit mac interface frame type paden state crcen state pad action crc action <9 bytes normal or tagged x x frame discarded by transmit mac control logic and debug counter incremented 9 to < tx min frame size reg. normal 0 0 no pad append 4 byte crc with error 1 9 to < tx min frame size reg normal 0 1 no pad append 4 byte crc with error 9 to < tx min frame size reg normal 1 0 pad with 0?s to tx min frame size reg value append 4 byte crc with error 2 9 to < tx min frame size reg normal 1 1 pad with 0?s to tx min frame size reg value 3 append 4 byte crc >= tx min frame size normal 0 0 no pad no crc append 1 packet is less than the minimum frame size. transmit mac will assert and error to the transmit pcs at the end of packet and add a corrupt crc to guarantee a downstream receiver will discard this packet. 2 same comment as above. 3 if frame is vlan tagged the p ad will increase by 4 bytes.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 329 document no.: pmc-2001304, issue 7 frame length at internal transmit mac interface frame type paden state crcen state pad action crc action reg. >= tx min frame size reg. normal 0 1 no pad append 4 byte crc >= tx min frame size reg. normal 1 0 no pad no crc append >= tx min frame size reg. normal 1 1 no pad append 4 byte crc 13.14 ethernet frame transmit errors the pm3392 device will use the 64-bit error block as defined in table 49-1 in the 802.3ae standard, to indicate a transmission error to its peer entity across the ethernet media. 13.14.1 transmit frame error catalysts the minimum frame length at the transmit system interface of the txxg for propagating an error indication is 9 bytes. any frame indication forwarded by the pl4 system side via the eflx that has a length less than 9 bytes will be discarded by the transmit control logic internal to the txxg: hence, no external ma c carrier event will be signaled. the catalysts for frame transmission with error ar e listed below. at least one catalyst needs to be true for asserting a frame transmit error on the ethernet media: 1. if the pl4 system sourcing device asserts an end-of-packet status of abort during egress frame transfer (pm3392 device pins tdat[15:0] +/-, tctl+/-). this error indication is forwarded on to the internal txxg transmit interface. 2. if the pl4 incoming data word parser (in th e pl4idu logic) indicates that the packet should be aborted. this could be either because a pl4 bus error occurred (case eop abort) or because a pl4 bus error was detected (case eop abort). this error indication is forwarded on to the internal txxg transmit interface. 3. if the egress frame is considered short (see note below), long, or having an internal transmit mac error (i.e. transmit underrun). another way of stating this is that the frame is transmit with an error indication if the mac sublay er within the txxg detects a transmit frame having a status that will be interpreted by the peer device across the ethernet link as erred. note: short frames at the txxg internal tr ansmit system interface will assert the error propagation character only if the following register settings are in effect: o the paden bit is set to logic 0 note that detection of an error in the framechecksequence (fcs) field of a frame during transmission does not result in a transmit error indication on the ethernet media for the given channel. restated, an fcs error detected during frame transmission is not a catalyst for asserting the error_propagation character. the frame is expected to be detected during the frame receive process on the peer en tity across the ethernet media.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 330 document no.: pmc-2001304, issue 7 transmit underrun an internal transmit mac error is detected if the transmit fifo internal to the txxg at the eflx interface underruns: that is, the fifo goes empty before an internal end-of-packet indicator is read. in a typical system application transmit underrun will not occur as long as the peer device that is sourcing traffic on the pl4 bus is able to maintain an adequate rate of data transfers. as previously described, the egr ess fifo interface on the pm3392 device maintains a cut-through threshold that is used for determin ing whether data is to be forwarded on to the txxg for transmission on the ethernet media. for a system application that is operating on standard ethernet sized frames (those having a maximum length of 1522 bytes), the cut-through threshold can be set for 1536 bytes (see eflx cut-through threshold register), thereby guaranteeing that frames will not be transferre d from the egress fifo to the txxg until the complete frame is buffered. internal to the pm 3392 device, the rate of data transfer from the txxg for transmit data is limited by the 645 mhz device reference clocks, with two octets of data being transferred every re ference clock period. the difference in internal clock rates between the txxg transmit interface and the egr ess fifo accounts for at most a two-byte contribution to the transmit underrun calculation: 9600 bytes * 8-bits/byte * 200 ppm = 15.4 bit-times therefore, for a system application that is transferring ethernet frames of 9600 bytes the requirement to prevent underrun is, on a frame-b y-frame basis that the traffic sourcing device must transfer the remaining (frame_length ? cut-through) number of data bytes within the amount of time that it takes to impress the frame data on the ethernet media, not counting the inserted ifg and preamble times. for example, to guarantee that transmit underrun does not occur on a frame of 9600 bytes - assuming [1] that the 645 mhz reference clock has an approximate 1.5 ns period; [2] that the eflx cut-through threshold is set for 1536 bytes; [3] that there are no errors detected on the pl4 bus incoming word stream at the pl4idu block of the pm3392 device - the system interface egress device must transfer the last 8604 (i.e. 9600-1536) bytes of the frame on the pl4 bus within a 6 us (8064/2 * 1.5 ns) time window starting from the time that the 1536 th byte was transferred on the pl4 bus. the response of the txxg to transmit underrun is: 1. all bytes that had been forwarded to th e txxg at the time the underrun occurred will be impressed on the xsbi pins as long as the underrun condition occurs after the 9 th byte of the frame (if before 9 bytes, the data is discarded as described previously since there is not a valid ethernet da, sa, and ieee/type field in the frame) 2. at the point of underrun, the error is signaled on the xsbi pins using the ethernet transmit frame error protocol described below 3. all subsequent data sent by the eflx to the txxg will be discarded until the next valid start-of-packet flag is set.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 331 document no.: pmc-2001304, issue 7 13.14.2 ethernet transmit frame error protocol all frames that are transferred by the mac inte rface with a transmit error calculation exhibit the following behavior: ? a 64-bit control block is formed with the e rror control code as defined in table 49-1 in 802.3ae, all eight character locations. in the event that the frame being transmit is de tected as having an error at the input transmit control interface of the txxg and prior to an end-of-frame indicator, the frame will be truncated by the transmit control logic and th e mac layer will be signaled to assert transmit error. the following transmit errors are det ectable at the txxg transmit control interface and can result in truncation during transmission: 1. an eop abort status is detected on the pl4 system interface. this eop abort could have been indicated on the pl4 bus as an end- of-packet status of abort or it could be the result of the pl4idu logic detecting a word parsing error. 2. transmit underrun is detected 3. tx max frame length is violated 13.15 frame length support the pm3392 supports a programmable maximum threshold for mac frame length and a programmable forwarding threshold; the thresholds in both the ingress and egress directions are fully independent and programmable. in addition, there is a minimum fixed size of a frame that is supported in each direction; frames of less than this fixed size are always discarded. the pm3392 supports jumbo frames up to 9600 bytes in both the ingress and egress directions. 13.15.1 ingress (ethernet receive) frame length the rxxg supports a minimum ingress frame fragment size of 9 bytes (fixed) and a programmable maximum ingress frame size of up to 9600 bytes. the minimum frame fragment size requirement is the result of supporting address filtering: any received frame that has less than 9 bytes w ill be not be forwarded on from the rxxg. if a frame fragment of less than 9 bytes is received it will be filtered and the proper receive statistics information on the frame recorded. the rxxg minimum receive frame length register control the minimum size of the ingress frame. if the frame is less than the programmed min frame length the frame will be treated as a short or runt frame depending on if the frame had a non-erred or erred fcs respectively. the short or runt frame is then filtered and the appr opriate status vector is generated for the frame to update the ethernet statistics.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 332 document no.: pmc-2001304, issue 7 the rxxg maximum receive frame length register controls the maximum size of the ingress frame. if the frame is greater than th e programmed size the frame will be treated as a long or jabber frame, depending on if the frame had a non-erred or erred fcs respectively. if the length of the received frame is greater than the rxxg receive maximum frame length then the incoming frame is truncated to the lengt h programmed in that register and the frame is flagged as erred. the rxxg receive fifo threshold register sets the forwarding threshold used for ingress frame gathering and error reporting. frames are passed from the rxxg to the pl4 ingress fifo if an end-of-frame indication has been r eceived by the rxxg or if the number of bytes received by the rxxg is greater than the rxxg receive fifo threshold register. ethernet mac frames that are received as erred and that are forwarded on to the system interface (the pos-phy level 4 interface) cause the affected p acket to have an end-of-packet status of abort in the pl4 payload control word following th e last byte of the ethernet frame that is in the pl4 data word. this mechanism provides for two different fra me error reporting capabilities. first if the forwarding threshold is set higher than the received frame size the rxxg will drop and not forward erred frames. second if the forwarding threshold is set lower than the received frame size the rxxg will immediately start passing the incoming frame as soon as the threshold is reached. in this case the rxxg passes the state of the receiveerror flag to the downstream logic and the pm3392 will assert an end-of-packet status of abort during data transfer on the pl4 bus. there is no additional frame forwarding thres hold register in the ingress datapath of the pm3392 device other than the rxxg receive fifo threshold register. 13.15.2 receive frame length checking the pm3392 device supports frame length checking based on the value of the sixteen bit length/type field in the received frame. recei ve frame length checking is enabled by setting the flchk bit of the rxxg configuration 1 register , to a logic 1. if flchk is set to a logic 1, a received frame will fail the frame length check if the length/type field of the frame has a length interpretation and the number of received oc tets in the data frame less 18 (length field indicates the number of mac client data octets and does not count the 6 octets of destination address nor 6 octets of source address nor 2 octets of length/type field itself nor 4 octets of fcs) is greater than the numeric value of the length/type field. the length/type field of a receive frame has a length interpretation on th e pm3392 device if the ethernet frame is untagged (as per 802.3 standard, clause 3.5.4- ?t he length/type field of a tagged mac frame always uses the type interpretation?) and the lengt h/type field is greater than or equal to 0 decimal and less than or equal to 1500 decimal.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 333 document no.: pmc-2001304, issue 7 13.15.3 egress (ethernet transmit) frame length the eflx fifo cut-through threshold register sets the forwarding threshold used for egress frame gathering on a per-channel basis. packets passed to the pm3392 on the pl4 bus will be gathered in the egress fifo until an end of packet indication or until the number of bytes transferred to the pm3392 and present in th e egress buffer are greater than or equal to the eflx fifo cut-through threshold register (this register counts in terms of 16-byte data blocks). this forwarding threshold allows frame buffering required to ensure that a frame will not underrun once frame transmission begins on the ethernet link. the txxg supports a minimum frame length of 9 bytes (fixed) at the transmit system interface. the programmable maximum egress frame size is 9600 bytes. a frame that is received with a length of less than 9 bytes, from the pl4 system side (i.e. via the eflx) will be discarded, regardless as to the setting of the paden and crcen mode bits. frames having a length of 9 or more bytes at the system interface will always be transferred by the ethernet mac and impressed on the pm3392 xsbi pins. in order to aid diagnostics, a count of frames that are discarded in the txxg transmit interface because they had a length of less than 9 bytes is maintained in the txxg filter error count register. the minimum frame size on the egress channel for mac frames after any optional padding or fcs appending is 64 bytes: this is a fixed limit. if a frame is transferred to the txxg transmit interface having a length of between 9 and 64 bytes after any optional padding or fcs appending, then the frame will be transmit as a s hort erred frame: the error control block will be sent at the end of the frame. the txxg transmit max frame length register controls the maximum size of the egress frame. the transmit max frame length register specifies the maximum number of bytes transmitted before truncation in an outgoing non-tagged ethernet frame (in the 802.3-2000 specification, this parameter is termed maxunt aggedframesize). the default setting of this register is 0x05ee (1518 decimal), which results in a maximum frame size before frame truncation of 1518 bytes if untagged and 1522 bytes if vlan tagged. frames that have exceeded the setting of transmit max frame length are truncated and have the error control block impressed at the end-of-packet. vlan tagged frames have a 4 byte offset (i.e. 1522 bytes by default) before being considered as violating the frame length setting. the length of the frame as transmit by the ethe rnet mac is determined by the length of the frame transferred by the egress fifo, the setting of the paden and crcen mode bits (as described in the section ?mac transmit padding and crc generation?), and the value of the txxg transmit max frame length register. 13.16 frame data and byte format the pm3392 transfers octets of ethernet data frames in the same order as they are transmitted and received on the ethernet media. as noted in the ieee std 802-1990 (local and metropolitan area networks: overview and architecture):
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 334 document no.: pmc-2001304, issue 7 1. the transmission of data for ieee 802.3 occurs lsb (least significant bit) first. this is true for the entire packet, lan mac address fi elds (source and destination), mac-specific fields (e.g. length/type field in ieee 802.3 lans) and the mac information field. (see also 802.3 standard, clause 3.3). 2. the 48-bit address (universal or local) is represente d as a string of six octets. the octets are displayed from left to right, in the order that they are transmitted on the lan medium, separated by hyphens. each octet of the address is displayed as two hexadecimal digits. the bits within the octets are transmitted from le ft to right as shown below. in the display of octets, the first bit transmitted of each octe t on the lan medium is the lsb of that octet (e.g. i/g address bit is lsb of octet 0). the organizationally unique identifier is contained in octets 0,1,2 with octets 3,4,5 being administered by the assignee. the example given in std 802-1990 is: table 23 std 802-1990, figure 5-3 universal address octet 0 1 2 3 4 5 0011_0101 0111_1011 0001_0010 0000_0000 0000_0000 0000_0001 ^ first bit transmitted on the lan m edium (also the i/g address bit). the hexadecimal representation of this example is: ac-de-48-00-00-80 this hexadecimal representation is of ten referred to as the canonical format. for the purposes of the pm3392 engineering docu ment, the address example given above in the std 802-1990 is represented as follows: da[0] is the 1st bit on the lan medium: 0 da[1] is the 2nd bit on the lan medium: 0 da[2] is the 3 rd bit on the lan medium: 1 da[3] is the 4th bit on the lan medium: 1 da[4] is the 5th bit on the lan medium: 0 da[5] is the 6th bit on the lan medium: 1 da[6] is the 7th bit on the lan medium: 0 da[7] is the 8th bit on the lan medium: 1 da[8] is the 9th bit on the lan medium: 0 da[9] is the 10th bit on the lan medium: 1 da[10] is the 11th bit on the lan medium: 1 da[11] is the 12th bit on the lan medium: 1 da[12] is the 13th bit on the lan medium: 1 da[13] is the 14th bit on the lan medium: 0 da[14] is the 15th bit on the lan medium: 1 da[15] is the 16th bit on the lan medium: 1 and so forth
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 335 document no.: pmc-2001304, issue 7 da[40] is the 41st bit on the lan medium: 0 da[41] is the 42nd bit on the lan medium: 0 da[42] is the 43rd bit on the lan medium: 0 da[43] is the 44th bit on the lan medium: 0 da[44] is the 45th bit on the lan medium: 0 da[45] is the 46th bit on the lan medium: 0 da[46] is the 47th bit on the lan medium: 0 da[47] is the 48th bit on the lan medium: 1 the pm3392 will represent the address shown above (example in figure 5-3 of std 802-1990: ac-de-48-00-00-80) as da[7:0] = ac da[15:8] = de da[23:16] = 48 da[31:24] = 00 da[39:32] = 00 da[47:40] = 80 13.16.1 frame data and byte format on ethernet line side bit-in-byte ordering in the 802.3 et hernet standard is bit 0 (least significant bit) to bit 7 (most significant bit) with bit 0 being the first bit transf erred on the ethernet media. ethernet data is always transmitted and received via the mac line side in the following format. bits are transmitted and received from the top to bottom a nd from left to right. for example, for the destination address (da[47:0]), bit da[0] is tran smitted first and bit da[47] is transmitted last.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 336 document no.: pmc-2001304, issue 7 table 24 mac frame format 7 octets preamble 1 octet sfd 6 octets destination address 6 octets source address 2 octets length/type mac client data pad 4 octets frame check sequence extension least significant bit (first on ethernet media) most significant bit (last on ethernet media) b 0 b 7 octets within frame transmitted top to bottom
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 337 document no.: pmc-2001304, issue 7 13.16.2 frame data and byte format at pl4 interface bit in byte ordering within the entire pl4 data pa th is from bit 7 (most significant bit) to bit 0 (least significant bit). in the ingress direction, the first byte of the frame that is received on the ethernet line side is impressed on the pl4 rdat[ 15:8] byte lane, with the most significant bit aligned to rdat[15]. likewise in the egress directi on, the first byte of the frame that is to be transmit on the ethernet line side is impressed on the pl4 tdat[15:8] byte lane, with the most significant bit aligned to tdat[15]. two examples are provided: one for a non-vl an tagged ethernet frame having a length of 1518 bytes (so the ieee correct length/type field of the frame is 05-dc) and one for a vlan tagged ethernet frame. table 25 pm3392 data order on pl4 interface, non-vlan ethernet frame bits 15:8 bits 7:0 da[7:0] da[15:8] da[23:16] da[31:24] da[39:32] da[47:40] sa[7:0] sa[15:8] sa[23:16] sa[31:24] sa[39:32] sa[47:40] length/type[7:0]: 0x05 length/type[15:8] 0xdc data[7:0] data[15:8] data[23:16] ? ? ? fcs[24:31] 1st octet of frame check sequence as received on ethernet media. as per 802.3 clause 3.2.8, the fcs is impressed on the media with bit x31 first, bit x30 2 nd , and so on with bit x0 being transmit last, rdat[15:8] corresponds to bits [x24,x25,x26,x27,x28,x29,x30,x31]. fcs[16:23] 2nd octet of frame check sequence as received on ethernet media. as per 802.3 clause 3.2.8, the fcs is impressed on the media with bit x31 first, bit x30 2 nd , and so on with bit x0 being transmit last, rdat[7:0] corresponds to bits [x16,x17,x18,x19,x20,x21,x22,x23]. fcs[8:15] 3rd octet of frame check sequence as received on ethernet media. as per 802.3 clause 3.2.8, the fcs is impressed on the media with bit x31 first, bit x30 2 nd , and so on with bit x0 being transmit last, rdat[15:8] corresponds to bits [x08,x09,x10,x11,x12,x13,x14,x15]. fcs[0:7] 1st octet of frame check sequence as received on ethernet media. as per 802.3 clause 3.2.8, the fcs is impressed on the media with bit x31 first, bit x30 2 nd , and so on with bit x0 being transmit last, rdat[15:8] corresponds to bits [x00,x01,x02,x03,x04,x05,x06,x07].
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 338 document no.: pmc-2001304, issue 7 table 26 pm3392 data order on pl4 interface, vlan ethernet frame type bits 15:8 bits 7:0 comment da[7:0] da[15:8] octets 1,2 da[23:16] da[31: 24] octets 3,4 da[39:32] da[47: 40] octets 5,6 sa[7:0] sa[15:8] octets 7,8 sa[23:16] sa[31:24] octets 9,10 sa[39:32] sa[47:40] octets 11,12 0x81 0x00 vlan qtag prefix tag_control [7:0] tag_control [15:8] where the 12 bit vid field is given by the most significant 12 bits of tag_control; cfi bit is tag_control[4], and user_priorityis tag_control[7:5]. length/type[7:0] length/type [15:8] mac client length/type data[7:0] data[15:8] octets 19,20 data[23:16] ? octets 21,22 ? ? ? fcs[24:31] fcs[16:23] fcs[24:31] is the first octet of fcs impressed on the ethernet media fcs[8:15] fcs[0:7] fcs[0:7] is the fourth octet of fcs impressed on the ethernet media 13.16.3 ethernet frame segmentation on the pl4 bus system interface the pm3392 device in the ingress direction makes efficient usage of pl4 bus transfers from the ingress fifo logic. scheduling by the pl4mos is not guaranteed to be done at a frame boundary. the pm3392 device in the ingress direc tion cannot be programmed to guarantee that entire ethernet frames will be transmit contiguously. note that in the case that the rxxg marked the ingress ethernet frame with an err delimiter, then the frame will be transferred on the pl4 bu s and terminated with a eops[1:0] status of eop_abort). because of the encoding of the eop by the pl4 bus specification in this manner, it is impossible for the pl4 peer entity to determine the delimited length of the erred frame to within one byte. that is, the pl4 p eer entity does not know whether one or two bytes of the frame terminated with eop_abort were received at the rxxg link interface. 13.16.4 example of data representation, from ethernet physical packet to pl4 bus interface the following example shows how a physical packet corresponding to a 64 byte mac data frame would appear on the ethernet media and when transferred on the pl4 bus interface. this holds true for the ingress direction (eth ernet receive media to pl4 rdat[15:0], rctl pins) and egress direction (pl4 tdat[15:0], tctl pins to ethernet transmit media).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 339 document no.: pmc-2001304, issue 7 this example utilizes a 64-byte ethernet data frame that is represented in canonical format as: da = 12-34-56-78-9a-bc sa = 01-23-45-67-89-ab length/type field = 0c-0d (so type interpretation) mac client data = 0e-0f-10-11-12-13-14-15- 16-17-18-19-1a-1b-1c-1d- 1e-1f-20-21-22-23-24-25- 26-27-28-29-2a-2b-2c-2d- 2e-2f-30-31-32-33-34-35- 36-37-38-39-3a-3b framechecksequence field = fd-c9-0f-e2 this is also the representation of the frame at the reconciliation sublayer (e.g. xgmii): table 27 ten gigabit ethernet frame example ethernet media serial bit stream (first -> last) pm3392 octet internal representation pl4 bus dat[] pins and databurst cycle pm3392 interpretation /s/ start_of_packet internal pcs replaces /s/ with the first preamble octet: 0101_0101 not transferred start_of_packet: physical packet only so not transferred on pl4 bus 10101010 0101_0101 not transferred 2 nd octet of preamble 10101010 0101_0101 not transferred 3rd octet of preamble 10101010 0101_0101 not transferred 4th octet of preamble 10101010 0101_0101 not transferred 5th octet of preamble 10101010 0101_0101 not transferred 6th octet of preamble 10101010 0101_0101 not transferred 7th octet of preamble 10101011 1101_0101 not transferred sfd (start frame delimiter) physical packet only so not transferred on pl4 bus 01001000 0001_0010 dat[15:8], cycle 1 destination address [7:0] 00101100 0011_0100 dat[7:0], cycl e 1 destination address [15:8] 01101010 0101_0110 dat[15:8], cycle 2 destination address [23:16] 00011110 0111_1000 dat[7:0], cycl e 2 destination address [31:24] 01011001 1001_1010 dat[15:8], cycle 3 destination address [39:32] 00111101 1011_1100 dat[7:0], cycl e 3 destination address [47:40] 10000000 0000_0001 dat[15:8], cycle 4 source address [7:0] 11000100 0010_0011_ dat[7:0], cy cle 4 source address [15:8] 10100010 0100_0101 dat[15:8], cycl e 5 source address [23:16]
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 340 document no.: pmc-2001304, issue 7 ethernet media serial bit stream (first -> last) pm3392 octet internal representation pl4 bus dat[] pins and databurst cycle pm3392 interpretation 11100110 0110_0111 dat[7:0], cy cle 5 source address [31:24] 10010001 1000_1001 dat[15:8], cycl e 6 source address [39:32] 11010101 1010_1011 dat[7:0], cy cle 6 source address [47:40] 00110000 0000_1100 dat[15:8], cycle 7 length/type field [7:0] 00110000 0000_1100 dat[15:8], cycle 7 length/type field [7:0] 10110000 0000_1101 dat[7:0], cycl e 7 length/type field [15:8] canonical format of length/type field is 0c-0d 01110000 0000_1110 dat[15:8], cycle 8 mac client data, 1 st octet 11110000 0000_1111 dat[7:0], cycle 8 mac client data, 2 nd octet 00001000 0001_0000 dat[15:8], cycle 9 mac client data, 3rd octet 10001000 0001_0001 dat[7:0], cycle 9 mac client data, 4th octet ?? ?? ?? ?? 01011100 0011_1010 dat[15:8], cycle 30 mac client data, 45th octet 11011100 0011_1011 dat[7:0], cycle 30 mac client data, 46th octet 10111111 1111_1101 dat[7:0], cycle 31 framechecksequence, 1 st octet 10010011 1100_1001 dat[7:0], cycle 31 framechecksequence, 2 nd octet 11110000 0000_1111 dat[7:0], cycle 32 framechecksequence, 3 rd octet 01000111 1110_0010 dat[7:0], cycle 32 framechecksequence, 4 th octet canonical format of framechecksequence field is fd-c9-0f-e2 /t/ end_of_packet internal pcs appends /t/ on transmit, strips on receive not transferred end_of_packet: physical packet only so not transferred on pl4 bus 13.17 frame filtering the pm3392 has simple programmable options to filter or forward ingress frames to the upstream link device. the pm3392 receive addr ess filtering logic consists of eight exact- match mac/vid filters, one 64-bin hash based mu lticast filter and four address filtering control registers that control the state of the forwarding for each filter. each exact match filter includes one 48-bit mac address register and one 12-bit vi d register that can be programmed through the microprocessor interface to the appropriate valu es. the filter logic is controlled by the four rxxg address filter control registers. the host microprocessor has complete programmable access to all filtering features. each address filter option is per-port independently programmable.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 341 document no.: pmc-2001304, issue 7 13.17.1 group multicast address filtering in parallel with the exact address match, the pm3392 performs multicast filter lookups. within the pm3392 there resides a 64-bin hash based multicast filter consisting of one 64-bit mask register that is programmable from the microprocessor interface ( rxxg multicast hash register). this register is used in conjunc tion with a 6-bit value which is derived from bits [28:23] of the 32-bit crc computed over the d estination address. this 6-bit crc value is used to index into the 64-bit mask register. the 64-bit mask register is used to determine if a multicast address that hashes to a given bin w ill be accepted for forwarding the 64-bin hash based multicast filtering is enabled by the mhash_en bit in the rxxg address control 2 register. if the mhash_en bit is 0 then there is no hash based multicast filtering, however if mhash_en is 1 then hash based multicast filtering is enabled. the multicast hash filter operation operates only on multicast-type frames: those with the ieee group/functional bit set in the da of the frame (least significant bit of the most significant byte of the mac da. the final forward versus filter decision for a frame is a combination of both the group multicast address filter result and the results from the eight possible exact match filter operations. the 48-bit destination address of the received frame is passed through the standard 802.3 crc function in the same order in which the des tination address octets are received. making reference to the 802.3 specification, section 3.2.8 frame check sequence field, the crc function generating polyno mial and function is: g(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1 1. the first 32-bits of the frame (which is the first 32-bits of the destination address received) are complemented. 2. the 48 bits of the destination address are th en considered to be the coefficients of a polynomial m(x) of degree 47 3. m(x) is multiplied by x 32 and divided by g(x), producing a remainder r(x) of degree <= 31. 4. the coefficients of r(x) are considered to be a 32-bit sequence. bits [28:23] of the resultant 32-bit crc remainde r (call this crc_rem[28:23]) are used as the index into the mhash[63:0] register. the result of the group multicast address filter is logically represented by the variable mhash_accept: mhash_accept = (mhash_en == 1) & (mhash[ crc_rem[28:23] ] ==1); 13.17.2 exact match filter operation each of the eight exact match filters on the rxxg has four bits of associated configuration. these are found in the address filter control 1 register:
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 342 document no.: pmc-2001304, issue 7 1. adrfilt_ctrl[0] enables the exact match ope ration. if this bit is a logic 0 then the exact_match operation returns a logic 0. 2. adrfilt_ctrl[1] selects whether the source address or destination address of the received frame is used as the address for matching. 3. adrfilt_ctrl2] enables the match function to also compare the vlan tag vid[11:0] field of the receive frame if the two bytes following the receive frame source address are equal to the vlan tag id register 4. adrfilt_ctrl[3] is a configuration bit that determines whether an exact match will affect the variable accept or discard. the exact match filter operation is a two step process. the first step is to determine whether the address match criteria is logically true: ? exact_match is logic 1 if the exact matc h filter is enabled and the selected frame address (and optional vid field of a vlan tagged frame) are equal; otherwise, exact_match is logic 0. the second step is to set the exact_match_accept or exact_match_discard variable for the given (one of eight) ex act match filters based on the setting of adrfilt_ctrl[3]: ? exact_match_accept = exact_match & (adrfilt_ctrl[3] == 1); ? exact_match_discard = exact_match & (adrfilt_ctrl[3] == 0); 13.17.3 address filter accept / discard evaluation the final result of the address filter function is a single filter versus forward decision. the result of the group multicast address filter is comb ined with the result of the eight possible exact match filter operations to determine a fina l filter versus forward decision. the address filter logic can be configured so that a frame has a higher priority for being forwarded or filtered: this decision is based on the configur ation bit pmode in the address filter control 2 register. the results of the above filter operations are l ogically or?ed together and then evaluated based on pmode. let exact_match_accept[7:0] and exact_match_discard[7:0] represent the accept and discard variables fo r the eight independent exact match filters respectively. the final combined value of accept and discard for all address filters is logically: ? accept = (exact_match_accept[7:0] != 0) | mhash_accept; ? discard = (exact_match_discard[7:0] != 0);
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 343 document no.: pmc-2001304, issue 7 13.17.4 address filtering in non-promiscuous mode discard has priority over accept in non-prom iscuous mode (pmode a logic 0). a frame will be filtered only if accept is true and discar d is false. this is shown in the following table. it should be noted that if all filte rs are disabled, then all frames are filtered. table 28 address filter result in non-promiscuous mode pmode discard accept result of address filter function 0 0 0 filter frame 0 0 1 forward frame 0 1 0 filter frame 0 1 1 filter frame 13.17.5 address filtering in promiscuous mode accept has priority over discard in promiscuous mode (pmode a logic 1). a frame will be filtered only if discard is tr ue and accept is false. this is shown in the following table. it should be noted that if all filters are disabled , then all frames are accep ted. see clause 5.2.4.3 of 802.3 standard, function la yermgmtrecognizeaddress, for a reference to ?promiscuous?. table 29 address filter in promiscuous mode pmode discard accept result of address filter function 1 0 0 forward frame 1 0 1 forward frame 1 1 0 filter frame 1 1 1 forward frame 13.17.6 address filter programming the pm3392 frame filtering is programmed in the following manner. 1. disable receive ethernet traffic by setti ng rxen0 bit to 0 in the rxxg configuration register. note: when rxen0 is set to 0 there is a possible wait time for a frame to complete being received since the disable is a graceful disable and will only disable the port during an ifg period. 2. set the adrfilt_ctl[0] to 0 (disable state) for all exact match filters that need to be programmed or changed, including the mhash_en if programming or changing the multicast hash filters. 3. program all desired filters with the desired contents. o program the rxxg exact match address and rxxg match vid registers and respective rxxg address control 0 or rxxg address control 1 registers for the desired exact match options.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 344 document no.: pmc-2001304, issue 7 o program the rxxg multicast hash register with the desired bit mask and enable by programming the rxxg address filter control 2 register. 4. set the adrfilt_ctl[0] to 1 (enable state) for all exact match filters that need to be enabled, including the mhash_en if enabling the multicast hash filters. 5. enable receive ethernet traffic be setti ng rxen0 bit to 1 in the rxxg configuration register 13.17.7 receive address frame filtering byte order the address filtering registers are programmed a cer tain way to achieve an exact match on the da or sa. assume a da[47:0] = 0x01 0x02 0x03 0x04 0x05 0x06 where bit 40 of the da[47:0] is the multicast bit. the address filter register is broken up into three 16-bit registers labeled as high[15:0], mid[15:0], and low[15:0]. a byte swap needs to be performed when pr ogramming the address filter registers. hence: high[15:0] = 0x0605 mid[15:0] = 0x0403 low[15:0] = 0x0201 13.18 pause flow control the pm3392 allows 802.3 pause frames to be transmitted out the egress mac port based on three separate pause frame catalysts. these conditio ns are discussed further in this section but first a general description of the pm33 92 pause frame generation is provided. the transmit pause control frame logic responds to a transmit pause control request caused by one of these three catalysts: ? internal ingress fifo flow control (pause request based on iflx fifo fill level) ? external side-band pause request using the pause and paused pins . ? external host based pause request. each of the three catalysts, if enabled, are l ogically or?ed together to form a transmit pause control request to the txxg associ ated with a specific channel.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 345 document no.: pmc-2001304, issue 7 the pm3392 responds by entering a transmit p ause frame state. after waiting for any current frame transmission to end, a mac pau se control frame will be transmitted. the pause control frame is formatted as follows: table 30 pause control frame format octets frame field source of information 7 octets preamble auto-generated 1 octet sfd auto-generated 6 octets destination address auto-generated (01-80-c2-00-00-01) note that da[7:0] = 0x01, da[15:8] = 0x80?etc. 6 octets source address txxg station address register. user defined (txxg station address registers 3047h, 3048h, 3049h) 2 octets length/type field auto-generated (88-08) 2 octets opcode field auto-generated (00-01) 2 octets pausetimer field txxg pause timer register: by default ff-ff. defined by pause_time[0..15], register 304dh. 42 octets pad auto-generated 4 octets fcs auto-generated the pause frame is stitched together using register-based information and a series of auto- generated fields. as long as the pm3392 is in the transmit pause frame state the txxg will continually send pause control frames every time the internal txxg pause timer interval (pause_ival[15..0], register 304eh) counts down to zero. in this fashion the egress data- pipe will not be blocked for normal egress data traffic. the txxg pause timer and txxg pause timer interval registers are both programmable. by default the txxg pause timer register defaults to 0xffff and the txxg pause timer interval register defaults to 0xcfff. both are representative of the number of pause quanta used in the system. note that pause quanta is defined as 512 bit times. the txxg pause timer interval will reload to the programmed state when it reaches zero. it is the responsibility of the pause catalyst to hold the input to the txxg until norm al ingress traffic can be resumed. when the catalyst removes the request for pause the t xxg will send out a pause control frame with the pause timer value of zero. the three different pause frame catalysts are discussed in more detail below.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 346 document no.: pmc-2001304, issue 7 13.18.1 internal ingress fifo flow control the pos-phy ingress fifo logic (iflx) has a per-channel, programmable almost-full threshold: register iflx indirect full/almost full status & limit (indirect register 2210h) . when the ingress fifo fill level for the l ogical fifo exceeds the programmed almost-full threshold value an internal pause flow control request signal is asserted to the txxg. the txxg can be programmed to accept pos-phy ingress fifo pause flow control requests for egress traffic if the fctx bit is set in the txxg configuration register 1 (register 3040h). when enabled and the internal fifo pause flow control signal is asserted the txxg will commence sending 802.3 pause frames. the iflx logic continues to hold the internal fifo pause flow control request signal to the txxg un til the fifo fill level for the logical fifo of that channel is below the almost-emp ty threshold value programmed in the iflx indirect empty/almost empty status & limit register (indirect register 2211h). at this time the internal fifo pause flow control request signal is de-asserted informing the txxg to cease pause frame flow control by sending a pause control frame with the pause timer value of zero. the almost full threshold field (afth[13:0]) and almost empty threshold field (aeth[13:0]) in the iflx registers are in terms of the number of 128-bit words that can be held in the logical fifo . the table below is one example of what the iflx settings should be to guarantee a 3 km (for 9604 byte frames) and 5 km (for 1522 byte frames) loss less flow control domain. table 31 iflx fifo settings for lossless flow control register value lolim[9:0] (220eh) 0x0000 hilim[9:0] (220fh) 0x01fe afth[13:0] (2210h) 0x0e66 aeth[13:0] (2211h) 0x0e06 13.18.2 external side-band pause request the pm3392 has a sideband pause request signal or pause pin, ball aa29. asserting the pause signal (active high) places the txxg into a transmit pause frame state. the pause signal is to be asserted and held as long as mac control pause frames are required to be transmitted from the txxg. when normal frame reception is desired the pause signal is de- asserted. upon de-assertion a mac control frame with the pause timer value of zero will be transmitted. the pl4 bus protocol and implementation of th e output scheduling done by the pm3392 device using the pl4mos does not require intervention by an external agent to support low-level flow control and support of non-blocking operation. the pause signal is provided to allow an external agent to indicate a ?coarse? level of fl ow control independent of that provided by the internal ingress fifo flow control mechanism.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 347 document no.: pmc-2001304, issue 7 13.18.3 external host based pause request the pm3392 allows an external microprocessor to set a register bit to initiate a pause flow control request on a per-channel basis. this is done via the hostpause bit in the txxg configuration 1 register , (register 3040h). when the hostpause bit is set to logic 1 the txxg is placed in a transmit pause frame state. when normal frame reception is desired the hostpause register bit is de-asserted by settin g it to logic 0. pause frames are formatted based on the pause_time[15..0] value (regist er 304dh) and the pause_ival[15..0] value (register 304eh). upon de-assertion of hostpause a mac control frame with the pause timer value of zero will be transmitted. the pl4 bus protocol and implementation of th e output scheduling done by the pm3392 device using the pl4mos does not require intervention by an external agent to support low-level flow control and support of non-blocking operation. the hostpause register bit is provided to allow an external agent to indicate a ?coarse? leve l of flow control indepe ndent of that provided by the internal ingress fifo flow control mechanism. 13.18.4 reception of 802.3 pause frames as per the 802.3-2000 standard a valid pause frame shall contain following for the pm3392 to respond to the received pause mac control frame: 1. the globally assigned 48-bit multicast address (01-80-c2-00-00-01) or the unicast station address of the mac. 2. the length/type field = 8808 3. the pause opcode of 0001 4. a non-zero value in the pause timer field as per the 802.3-2000 standard only the length/type field and the opcode is needed to increment the pausemacctrlframesreceived, regardless of the da field. the pm3392 can be programmed to handle ingress pause control frames in the manner as outlined below. this programming is done via the parf bit in the rxxg configuration 1 register (register 2040h) and the fcrx bit in the txxg configuration 1 register (register 3040h). the parf bit programs whether or not control frames are passed to the upper layer device. the fcrx bit allows the mac control sub-la yer to respond to a received pause control frames by pausing the transmitter fro m transmitting data frames (this response is referred to as ?executed? in the following table). table 32 pause frame programmable control parf fcrx pm3392 action 0 0 pause frames are ignored and dropped at the pm3392 level. 0 1 pause frames are executed but ar e not passed to the upper layer. 1 x pause frames are ignored and forwarded to the upper layer device.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 348 document no.: pmc-2001304, issue 7 please note as per 802.3-2000 that if the pm3392 is currently executing reception of a pause frame and is currently blocking the data-path from transmission of mac data frames (i.e. normal data traffic) that mac control pause frames can still be sent. while the txxg has paused transmission of data frames, the paused pin, ball g9, will be asserted high. 13.19 ethernet mac receive fifo overrun condition the 802.3 specification defined mac control pause frames to inhibit transmission of mac data frames between two full-duplex peer ethe rnet devices across the ethernet media. however, support of ethernet mac control pause frames by a device that is a peer of the pm3392 device is an optional feature and so is not guaranteed to be supported on the peer device. in addition, a given application may use the pm3392 device in a manner that does not guarantee loss-less flow control (as described elsew here in the operation section, loss-less flow control is a function of the round-trip length of the fiber between the peer ethernet devices, the maximum frame size of the application, the provisioned amount of buffer space in the pm3392 device for the channel, and the response time of the peer device to the pause frame request and subsequent cessation of frame transmission). this section describes the behavior of the pm3392 ethernet mac (rxxg) to a receive fifo overrun condition. the response of the ethernet mac receive fifo to a overrun condition depends upon whether any of the data from the frame has been tran sferred to the downstream ingress fifo. as mentioned earlier, frame data transfer from the rxxg receive fifo can start either at an end- of-frame indication or when the number of bytes in the frame exceeds the rxxg receive fifo threshold . an ethernet mac receive fifo overrun condition o ccurs if the fifo is full and data continues to be received from the xsbi interface(this woul d be data from within an ethernet mac data frame). the actual fifo buffer used by the r xxg receive logic does not overflow: the internal pointers used for determining the location in th e fifo to read and write are prevented from actually overrunning. instead frame data is discar ded until there is sufficient buffer space in the receive fifo for the next frame and recepti on of subsequent frames resumes on a start-of- frame boundary. frame data transfer to ingress fifo had not started when ethernet mac receive fifo overrun occurs the receive control logic in the rxxg is res ponsible for the detection and recovery from a receive fifo overrun condition. if the overrun is detected before any data from the frame is transferred to the ingress fifo (which will always be the case if the received frame size is less than the rxxg receive fifo threshold) the receive control logic will flag the frame as an overrun frame and it will be discarded in its entir ety without being transferred to the ingress fifo. this is a countable event in the mstats receive counter frameslostduetointernalmacerror. the rxxg will re-synchronize to the next start of a physical packet (preamble/sfd delimiter) and c ontinue ethernet frame reception. if a receive fifo overrun condition occurs again, the response of the rxxg is identical to that described above until there is sufficient buffer space to accept either the entire frame or until the number of bytes of the received frame exceeds the rxxg receive fifo threshold. note that reception resumes on a start-of-frame boundary.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 349 document no.: pmc-2001304, issue 7 frame data transfer to ingress fifo started when ethernet mac receive fifo overrun occurs in the case that the receive fifo has starte d transferring data when the overrun condition occurs, the receive control logic will flag the frame in transfer as an overrun frame and discard all subsequent data from the frame until the ne xt start-of-frame boundary is detected. the frame in transfer when the overrun co ndition occurs (which is after the rxxg receive fifo threshold has been exceeded), will assert an internal receive error status signal to the ingress fifo. on the pl4 bus output interface (devi ce pins rdat[15:0]+/-, rctl+/-) the frame will be truncated at the location that the overrun occurred within the rxxg receiver and the frame will be marked as erred by having a pl4 end-of-packet status of abort. as discussed previously, this is a countable event in the mstats receive counter frameslostduetointernalmacerror. the rxxg will re-synchronize to the next start of a physical packet (preamble/sfd delimiter) and c ontinue ethernet frame reception. if a receive fifo overrun condition occurs again, the response of the rxxg is identical to that described above until there is sufficient buffer space to accept either the entire frame or until the number of bytes of the received frame exceeds the rxxg receive fifo threshold. note that reception resumes on a start-of-frame boundary. 13.20 using the performance monitoring features the pm3392 has associated with it an mstat bl ock that is used to accumulate ethernet specific counts for supporting management ag ents such rmon, snmp, and etherlike interfaces. the mstat provides counter width support for compliance with 802.3-2000 rollover requirements of 58 minutes, except the octetsreceived, octetsreceivedok, octetstransmitted, octetstransmittedok . these counters will rollover in approximately 15 minutes. the mstat supports full system probing capability via the use of full counter snapshot to shadow registers. the ethernet statistics counters maintained on the pm3392 device can be transferred to shadow registers by writi ng to logic 1 the snap bit of the mstat control register. this supports software polling of the mstat registers with a snapshot being taken at fixed time intervals; the data can then be r ead out of the shadow registers as a background software process over the pm3392 microprocessor interface. incorporated into the mstat block is a fully programmable interrupt array enabling per counter rollover monitoring with interrupt reporting. this supports customer software that requires an ?on-demand? read of the ethernet statistics. 13.21 interrupt handling the pm3392 signals the host processor via the use of the intb active low pin. when intb is asserted (logic 0) the host processor can interroga te the pm3392 for the source of the active interrupt by reading the pm3392 master interrupt status register: this identifies the interrupt source at the block level. further register accesses are required to the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. reading of the pm3392 master interrupt status register has no side-effects. interrupt status is set to logic 1 to indicate a pending interrupt of the specified type. the interrupt signal is asserted only if the interrupt status is true and the interrupt source is not masked.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 350 document no.: pmc-2001304, issue 7 to clear an interrupt the host processor must ac knowledge the interrupt s ources. this is done by reading the block-level interrupt source as dec oded by the master interrupt status register. a read from the block-level interrupt source will cl ear the block level interrupt. note that there may be more than one block level interrupt asser ted. to clear the device level interrupt all block level interrupts must either be cleared or masked off. every block level interrupt source has a corresponding interrupt mask bit. 13.22 jtag support the pm3392 supports the ieee boundary scan sp ecification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo used to control the tap controlle r and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 351 document no.: pmc-2001304, issue 7 figure 24 boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test a ccess port controller mux dff select tri-state enable the boundary scan architecture consists of a ta p controller, an instruction register with instruction decode, a bypass register, a devi ce identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction re gister with instruction decode block is used to select the test to be executed and/or the regist er to be accessed. the bypass register offers a single-bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 352 document no.: pmc-2001304, issue 7 13.22.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 353 document no.: pmc-2001304, issue 7 figure 25 tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 a ll transitions dependent on input tms 0 0 0 0 0 1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 354 document no.: pmc-2001304, issue 7 test-logic-reset the test logic reset state is used to disable th e tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap c ontroller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instru ction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load pa rallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test regi ster maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latch es are used to control the device's outputs. the parallel output latches are update d on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 355 document no.: pmc-2001304, issue 7 boundary scan instructions the following is a description of the standard inst ructions. each instruction selects an serial test data register path between input, tdi and output, tdo. bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is place between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr st ate. primary device outputs can be controlled by loading patterns shifted in through input td i into the boundary scan register using the update-dr state. sample the sample instruction samples all the device i nputs and outputs. for this instruction, the boundary scan register is placed between tdi a nd tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to conn ect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out output, tdo using the shift-dr state. 13.23 receive pcs layer error handling this section describes the behavior of the rx pcs during error conditions and during a fault condition. the rx pcs conforms to the 802.3ae standard for all error and fault conditions as described in clauses 49 and 46 of the 802.3ae sta ndard. all errors that the rx pcs encounters are communicated to the rx mac by latching the error condition until the end of packet is received. all fault conditions are terminated in the rx pcs block (i.e. will not be propagated to the system interface).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 356 document no.: pmc-2001304, issue 7 the possible error conditions that exist are: rece ive state machine errors, invalid 66-bit blocks, error control code, loss of sync, bit error state machine. the possible fault conditions are local fault or remote fault. the sections to follow will describe that details of the error conditions and the fault conditions. 13.23.1 receive state machine errors the rx pcs follows the receive state machine in figure 49-14 of 802.3ae. when the receive state machine transitions to rx_e (error state) , the rx pcs will replace the payload with all 0?s, but still drive the byte_valid signals for all 8 bytes. the rx pcs will latch the error condition and when a good end-of-frame occurs, will drive the appropriate pcs layer error signal to the rx mac. figure 26 expected packet formats sop eop d a t a 1 byte 1 byte 14 bytes minimum sop sop d a t a 1 byte 1 byte missing eop 4 d a t a missing eop or sop 5 data eop d a t a d a t a missing sop 1 d a t a missing eop 2 data sop sop eop data n bytes runt invalid 16 bytes d a t a eop overflow eop 6 d a t a eop sop overflow sop 3 invalid invalid invalid d a t a sop d a t a eop d a t a typical valid packet sequences invalid packet sequences eop invalid
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 357 document no.: pmc-2001304, issue 7 13.23.2 invalid 66-bit blocks there are three types of invalid 66-bit blocks: ? the sync field has a value of 00 or 11 ? the type field contains a reserved value ? any control character contains a value not in table 49-1 of 802.3ae when the rx pcs encounters an invalid 66-bit block the receive state machine will transition to the rx_e(error) state. 13.23.3 error control code the 802.3ae defines an error control code to be ei ght control characters and its first character is an error control code (0x1e). this condition can only occur when the type field is 0x1e and the first control code (c0[6:0]) is 0x1e and the rest of the control codes (c1-c7) are either 0x0 or 0x1e. when this is encountered the receive st ate machine will transition to the rx_e(error) state. 13.23.4 loss of sync once the rx pcs has achieved the initial synchr onization there are two ways for the rx pcs to lose sync. if within receiving 64 66-bit blocks there are 32 or more invalid sync fields(00,11) or if the sync_err signal is asserted when a loss of sync occurs, the rx pcs will te rminate and error any packet that is being transferred across the system interface and assert the rx_los status signal and los status bit. the assertion of the los status bit can cause an interrupt to be generated if enabled. if the loss of sync is due to the assertion of sync_err a sync_err status bit will also be asserted. the assertion of the sync_err status bit can cause an interrupt to be generated if enabled. 13.23.5 bit error state machine the rx pcs monitors bit errors in the sync fi eld. the bit error state machine is defined in figure 49-12 of 802.3ae. the bit error state m achine uses an 125us timer to give a window for a high bit error indication. a high bit error is de fined as 16 bit errors within an 125us window. when a high bit error occurs the hi_ber status b it will be asserted, this can cause an interrupt to be generated if enabled. when the ber state machine goes into a hi_ber state the receive state machine will jump to the rx_init state cau sing no data to be transferred to the rx mac. the receive state machine will remain in the rx_init state until the hi_ber state is cleared. the 125us timer is a 14-bit counter that rolls over to 0 when the coun ter reaches the default done value. the default done value on reset is 20162 or 0x4ec2. the calculation for the 125us timer is 125us/6.2ns(period of sys_clkx2).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 358 document no.: pmc-2001304, issue 7 13.23.6 fault conditions fault signaling is communicated by using the de fined sequence ordered set in 802.3ae the rx pcs also includes part of the rs layer, ther efore the section in clause 46 link fault signaling also applies. local fault a local fault(lf) is defined as being one of the order set type control codes defined in figure 49-7 of 802.3ae with the d3 or d7 byte fiel d being 0x01. when at least 4 lf messages are received the rx pcs will assert the rx_lf status signal and assert the link fail status bit. the assertion of the rx_lf status signal or link fail status bit can cause an interrupt to be generated if enabled. after achieving a local fau lt state, when there is an absence of local fault messages for at least 64 sys_clkx2?s the rx pcs will de-assert rx_lf status signal and the link fail status bit. the local fault messag es are terminated in the rx pcs, only idle?s are passed to the rx mac. remote fault a remote fault(rf) is defined as being one of the order set type control codes defined in figure 49-7 of 802.3ae with the d3 or d7 byte field being 0x02. when at least 4 rf messages are received the rx pcs will assert the rx_rf status signal. the assertion of the rx_rf status signal can cause an interrupt to be generated if enabled. after achieving a remote fault state, when there is an absence of remote fault mess ages for at least 64 sys_clkx2?s the rx pcs will de-assert rx_rf status signal. the remote fau lt messages are terminated in the rx pcs, only idle?s are passed to the rx mac. 13.24 transmit pcs layer error handling this section describes the behavior of the tx pcs during error conditions and during a fault condition. the tx pcs conforms to the 802.3ae standard for all error and fault conditions as described in clauses 49 and 46 of the 802.3ae standard. the possible error conditions that exist are: transmit state machine errors, mac transmit errors, loss of sync from the rx pcs, hi_ber from the rx pcs. the possible fault conditions are local fault or remote fault. the sections to follow will describe that details of the error conditions and the fault conditions. 13.24.1 receive state machine errors the tx pcs follows the transmit state mach ine in figure 49-14 of 802.3ae. when the transmit state machine transitions to tx_e (error state), the tx pcs will insert the 66-bit error code as defined by the 802.3ae.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 359 document no.: pmc-2001304, issue 7 13.24.2 mac transmit errors the tx pcs will also insert the 66-bit e rror code when the tx mac asserts the system_error signal. the system_error si gnal is asserted when the tx mac has encountered an error. 13.24.3 loss of sync from the rx pcs when the rx pcs encounters a loss of sync the tx pcs will treat this as a local fault condition. when in a local fault condition th e tx pcs will hold off data from the tx mac and stream out the remote fault code altern ating between idle?s and remote fault until the local fault condition is cleared. 13.24.4 hi ber from the rx pcs when the rx pcs encounters a high bit error the tx pcs will treat this as a local fault condition. when in a local fault condition th e tx pcs will hold off data from the tx mac and stream out the remote fault code altern ating between idle?s and remote fault until the local fault condition is cleared. 13.24.5 local fault received from the rx pcs when the rx pcs receives the local fault code the tx pcs will treat this as a local fault condition. when in a local fault condition th e tx pcs will hold off data from the tx mac and stream out the remote fault code altern ating between idle?s and remote fault until the local fault condition is cleared. 13.24.6 remote fault received from the rx pcs when the rx pcs receives the remote fault code the tx pcs will treat this as a remote fault condition. when in a remote fault condition the tx pcs will hold off data from the tx mac and stream out idle?s until the remote fault condition is cleared. 13.25 mdio access the mdio block communicates between the host processor and an external mii physical device by means of a two wire interface. the mdio block produces a 2.5 mhz mdc (management data clock) clock by dividing down the system clock. the control information is synchronously driven by the mdio with respect to mdc and is sampled synchronously by the phy. status information is driven by the phy synchronously with respect to mdc and is sampled synchronously by mdio. this section describes how the host can use on-chip registers to access the external mii phy. the bit definitions and details of these register s are defined in the normal mode register description. there are four different opera tion namely address, write, read and read-post- increment.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 360 document no.: pmc-2001304, issue 7 13.25.1 mii address operation 1. check the busy bit in the status register (po ll the busy bit in the status register or wait for the busyi interrupt) make sure it is low. 2. program the port address, and device address for the particular mdio manageable device (mmd) to be accessed in the mmd phy address register. 3. program the ctlad register with the address of the register to be accessed by subsequent data transaction frame. 4. set the lctla bit in the mdio command register. this will initiate the mii address operation and the busy bit in the status register will be asserted until the operation is complete. 13.25.2 mii data write operation 1. transmit the address frame as specified in the previous section. 2. wait for the busy signal to be deasserted. 3. program the ctlad register with the control data to be transmitted. 4. set the lctld bit in the mdio command re gister. this will initiate the mii data write operation and the busy bit in the status register will be asserted until the operation in complete. 13.25.3 mii data read operation 1. transmit the address frame as specified above 2. wait for the busy signal to be deasserted. 3. set the rstat bit in the mdio command register. this will initiate the read operation and set the busy bit in the status register until the operation is complete. once the busy bit is deasserted read the mdio read status data register prsd. 13.25.4 mii rdinc operation 1. wait for the busy signal to be deasserted. 2. program the port address, and device address for the particular mdio manageable device (mmd) to be accessed in the mmd phy address register. 3. set the rdinc bit in the mdio command regi ster. this will initiate a post-read-increment- address operation and set the busy bit in the stat us register until the operation is complete. upon completion of the read operation the mmd will increment the address register by one. once the busy bit is deasserted read the prsd.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 361 document no.: pmc-2001304, issue 7 14 functional timing 14.1 pl4 interface data path and fifo status timing a timing diagram of the pl4 interface data path signals is shown in figure 27. this diagram is applicable to either the transmit or the receive interface. tctl/rctl is high when tdat[15:0]/rdat[15:0] contains control words. idle periods correspond to back-to-back control words. data and control words are upda ted on both the rising and falling edges of the tdclk/rdclk. the actual clock rate used in prac tice is determined by the application at hand (up to a maximum of 700 mhz data rate divided by 2). figure 27 pl4 interface data path functional timing idle idle idle idle data control data control data control control control data data data control data data tdclk / rdclk tdat [15:0] / rdat [15:0] tctl / rctl complete packets or shorter bursts (fragment of larger packets) may be transferred. the maximum configured payload data transfer size must be a multiple of 16 bytes. control words are inserted only between burst transfers. on ce a transfer has begun, data words are sent uninterrupted until end-of-packet or the burst tr ansfer size is reached, whichever comes first. the interval between the end of a given transfer and the next payload control word (marking the start of another transfer) consists of zero or more idle control words. the minimum and maximum supported packet lengths are determined by the application. for ease of implementation however, successive start- of-packets must occur not less than 8 cycles apart, where a cycle is one control or data word . the gap between shorter packets is filled with idle control words. payload data bytes are transferred over the interface in the same order as they would be transmitted or received on the line side. the most significant bits (msbs) of the constituent bytes correspond to bits 15 and 7. the byte with msb at bit 15 is transmitted or received first on the line side relative to the byte with msb at bit 7. on payload transfers that do not end on an even byte boundary, the unused byte (after the last valid byte) is set to all zeroes. figure 28 shows the pl4 interface fifo status functional timing for the s/uni-1x10ge device. fifo status information is sent periodically over tstat[1:0] from the s/uni-1x10ge to the link layer device, and over the rstat[1:0] from the link layer to the s/uni-1x10ge. the transmit and receive status channels ope rate independently of each other. stat[1:0]/rstat[1:0] is updated on the risi ng edge of tsclk/rsclk . tsclk/rsclk runs at a nominal rate of 1/8 th the data rate of the pl4 transmit/receive interface.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 362 document no.: pmc-2001304, issue 7 figure 28 pl4 interface fifo status functional timing round-robin period round-robin period msb[2] dip[1] lsb[2] msb[n] msb[1] lsb[1] msb[2] lsb[2] lsb[1] msb[1] lsb[n] dip[0] tsclk / rsclk tstat[1] / rstat[1] tstat[0] / rstat[0] the fifo status of each port is encoded in a 2- bit data structure as per pl4 specification. the port sequences on the transmit and receive interf aces may be configured differently from each other. the ?1 1? pattern is reserved for in-ba nd framing. it must be sent once prior to the start of the fifo status sequence. a dip-2 odd parity checksum is sent at the end of each complete sequence, immediately before the ?1 1? framing pattern. the dip-2 code is computed over all preceding fifo status indications sent after the last ?1 1? framing pattern as per pl4 specification. a continuous stream of repeated ?1 1? framing patterns may be sent to indicate an error condition. 14.2 xsbi functional timing this section shows the functional timing relati onship for the ingress and egress paths. no propagation delays are shown. figure 29 ingress timing diagram rxclk_p/n rxdata_p/n 7 system_clk rxdata_int_[7:0] system_clk2x byte n byte n byte n-1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 byte n+1 byte n+2 byte n-2 4 cycles 0
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 363 document no.: pmc-2001304, issue 7 figure 30 egress timing diagram txclk_src_p/n txclk_p/n system_clk system_clk2x byte n txdata_int[7:0] 7 byte n-1 txdata_p/n byte n+1 byte n+2 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 7 6 5 4 3 byte n byte n+1 byte n-2 4 cycles 2 1
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 364 document no.: pmc-2001304, issue 7 15 absolute maximum ratings maximum rating is the worst-case limits that the device can withstand without sustaining permanent damage. they are not indicat ive of normal mode operation conditions. table 33 maximum ratings storage temperature -40c to +125c supply voltage see table 40 below voltage on any pin see table 41 below static discharge voltage 1000 v latch-up current 100 ma dc input current 20 ma lead temperature +225c voltage of overshoot of duration <10ns on any pin (unless otherwise specified) -2.0v to vddo+2.0 v junction temperature under bias (correct operation not necessarily guaranteed) -40c to +125c table 34 core supply voltage specs process absolute min vdd [v] absolute max vdd [v] 0.18um cmos core supply -0.5 2.2 table 35 i/o supply voltage specs process absolute min vddo [v] absolute max vddo [v] min voltage on any pin vx [v] max voltage on any pin vx [v] 3.3v tolerant 3.3v supply vdd (core)- 0.5 4.0 -0.5 vddo +0.5
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 365 document no.: pmc-2001304, issue 7 16 d.c. characteristics t a = -40c to t j = +125c, v vddi = v vdditypical 5%, v vddo = v ddotypical 5% (typical conditions: t a = 25c, v vddi = 1.8v, v vddo = 3.3v, v avdl = 1.8v, v av d h = 3.3v) table 36 d.c. characteristics symbol parameter min typ max units conditions v vddi power supply 1.71 1.8 1.89 volts v vddo power supply 3.135 3.3 3.465 volts v avdl power supply 1.71 1.8 1.89 volts v avdh power supply 3.135 3.3 3.465 volts vil input low voltage 0.8 volt s guaranteed input low voltage vih input high voltage 2.0 volts guaranteed input high voltage vol output or bi- directional low voltage 0.1 0.4 volts guaranteed output low voltage at vddo=2.97v and iol=maximum rated for pad. voh output or bi- directional high voltage 2.4 2.7 volts guaranteed output high voltage at vddo=2.97v and ioh=maximum rated current for pad. vt- reset input low voltage 0.8 volts a pplies to rstb and trstb only. vt+ reset input high voltage 2.2 volts a pplies to rstb and trstb only. iilpu input low current -300 -120 - 10 a vil = gnd. notes 1 and 3. iihpu input high current -10 0 + 10 a vih = vddo. notes 1 and 3. iilpd input low current -10 0 + 10 a vil = gnd. notes 5 and 3. iihpd input high current -300 -120 - 10 a vih = vddo. notes 5 and 3. iil input low current -10 0 +10 a vil = gnd. notes 2 and 3. iih input high current -10 0 +10 a vih = vddo. notes 2 and 3. cin input capacitance 5 pf ta=25c, f = 1 mhz cout output capacitance 5 pf ta=25c, f = 1 mhz cio bi-directional capacitance 5 pf ta=25c, f = 1 mhz lvds receiver dc specifications (pins: tdclk+/-,tda t[15:0]+/-, tctl+/-) vicm lvds input common-mode range 0 2.4 v a pplies to lvds inputs.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 366 document no.: pmc-2001304, issue 7 symbol parameter min typ max units conditions |vidm| lvds input differential sensitivity 100 600 mv a pplies to lvds inputs. rin lvds differential input impedance 80 100 120 a pplies to lvds inputs. lvds output dc specifications (pins: rdclk+/-, rdat[15:0]+/-, rctl+/-) vloh lvds output voltage high 1375 1475 mv rload=100 1% vlol lvds output voltage low 925 1025 mv rload=100 1% vodm lvds output differential voltage 100 350 600 mv rload=100 1% vocm lvds output common-mode voltage 1125 1200 1275 mv rload=100 1% dc-coupled pecl: dc specification (pins: pl4_rclk+/-) vpecli+ input dc pecl high voltage vavdh ? 1.165 vavdh ? 0.955 vavdh ? 0.880 volts a pplies to pl4_rclk+/- inputs only. vpecli- input dc pecl low voltage vavdh ? 1.810 vavdh ? 1.700 vavdh ? 1.470 volts a pplies to pl4_rclk+/- inputs only. lvds xsbi dc specifications (pins: txdata1-4[0-3]+/ -, rxdata1-4[0-3]+/-) v i lvds input voltage range 900 1600 mv |vgpd| <50mv see note 4 v id lvds input differential voltage 100 600 mv |vgpd| <50mv see note 4 r in lvds differential input impedance 80 120 v od lvds output differential voltage 250 400 mv r load =100 1% v os lvds output offset voltage 1125 1375 mv r load =100 1% |v od | change in |v od | between ?0? and ?1? 50 mv r load =100 1% |v os | change in |v os | between ?0? and ?1? 50 mv r load =100 1% t r , t f 20%-80% rise and fall times 100 400 ps notes on d.c. characteristics: 1. input pin or bi-directional pi n with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor. 3. negative currents flow into the device (sinking) , positive currents flow out of the device (sourcing). 4. |vgpd| is the ground potential di fferential between pma client and pma
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 367 document no.: pmc-2001304, issue 7 5. input pin or bi-directional pin with internal pull-down resistor.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 368 document no.: pmc-2001304, issue 7 17 microprocessor interface timing characteristics t a = -40c to t j = +125c, v vddi = v vdditypical 5%, v vddo = v ddotypical 5% (typical conditions: t j = 25c, v vddi = 1.8v, v vddo = 3.3v) table 37 microprocessor interface multiplexed read timing symbol parameter min max units ts ar a ddress to valid read set-up time 10 ns th ar a ddress to valid read hold time 5 ns ts alr a ddress to latch set-up time 10 ns th alr a ddress to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 70 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to intb high 50 ns figure 31 microprocessor interface read timing valid tzrd tprd tzinth thlr tslr thalr tvl tsalr tvl thar tsar a[14:0] ale (csb+rdb) intb d[15:0]
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 369 document no.: pmc-2001304, issue 7 notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[15:0]). 3. a valid read cycle is defined as a logical and of the csb and the rdb signals while the wrb signal is not asserted. 4. in non-multiplexed address/data bus architec tures, ale should be held high so parameters ts alr , th alr , tv l , ts lr , and th lr are not applicable. 5. parameter th ar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1. 4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 vo lt point of the clock. table 38 microprocessor interface write access symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 370 document no.: pmc-2001304, issue 7 figure 32 microprocessor interface write timing valid thlw thdw tsdw tvwrtvwr tslw thalw tvl tsalw tvl thaw tsaw a [14:0] a le (csb+wrb) d[15:0] notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical and of the csb and the wrb signals. 2. in non-multiplexed address/data bus architec tures, ale should be held high so parameters ts alw , th alw , tv l , ts lw , and th lw are not applicable. 3. parameter th aw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1. 4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 371 document no.: pmc-2001304, issue 7 18 ac timing characteristics t a = -40c to t j = +125c, v vddi = v vdditypical 5%, v vddo = v ddo typical 5% (typical conditions: t a = 25c, v vddi = 1.8v, v vddo = 3.3v) 18.1 pl4 interface timing 18.1.1 interpretation of the spi-4-ii/pl4 standards for lvds electrical, jitter and skew specifications this section provides clarification and supplemental information regarding the electrical specifications of pmc-sierra?s pos-phy leve l 4 interface implemen ted on the xenon family of devices. the information provided in this sec tion is specific to pmc-sierra?s implementation of the pl4/spi-4 phase ii standard and provi des additional clarification of performance specifications outlined in the standards that are ambiguous or incomplete. lvds electrical the lvds electrical specifications for th e pmc pl4/spi-4-ii interfaces are given in table 39. it should be noted that the pl4/spi-4-ii standards just reference the ieee and tia lvds standards for the lvds electrical specifications . in some cases these two standards differ, as well as being different than the sfi-4-i standard. table 39 lvds electrical specifications symbol parameter comments typ units t r , t f input 20%-80% rise & fall times see notes 1 & 2 0.36 ui t r , t f output 20%-80% rise & fall times 175 ps notes: 1. same as the pl4/spi-4-ii standards. 2. rise/fall times are measured from the 20% to 80% thresholds 18.1.2 clock and data jitter methods 18.1.3 reference clock interface the data in table 40 and table 41 below is for the reference clock when in master mode. this data is not part of the pl4/spi-4-ii standards (no specifications are given for refclk input). table 40 reference clock timing speci fications for divby2 (pl4_refclk) symbol parameter min typ max units comments fd reference clock frequency 311 350 mhz dcref reference clock duty cycle 40 60 %
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 372 document no.: pmc-2001304, issue 7 djref reference clock deterministic jitter (pk-to-pk between fd/1000 & 8mhz) (pk-to-pk between fd/1000 & fd) 0.01 0.05 ui ui tjref reference clock total jitter (pk-to-pk between fd/1000 & fd) 0.10 ui trfref reference clock rise / fall times 1.0 ns not in the pl4/spi-4-ii standards notes on reference clock timing: 1. master mode and divby2 (refsel[0] = "1" & refsel[1] = ?0?). 2. the unit interval (ui) is the reciprocal of the symbol rate. 3. total jitter includes both deterministic jitter and ra ndom jitter. the random jitter is the total jitter minus the actual deterministic jitter. 4. values are measured with each pecl/lvds i nput dc coupled into a 50 ohm impedance (100 ohms differential impedance). 5. rise time is measured from the 10% threshold of the reference signal to the 90% threshold of the reference signal. 6. fall time is measured from the 90% threshold of the reference signal to the 10% threshold of the reference signal. 7. duty cycle and jitter are specified between different ial crossings of the 50% threshold of the reference signal. table 41 reference clock timing speci fications for divby4 (pl4_refclk) symbol parameter min typ max units comments fd reference clock frequency 155.5 175 mhz dcref reference clock duty cycle 40 60 % djref reference clock deterministic jitter (pk-to-pk between fd/500 & 8mhz) (pk-to-pk between fd/500 & 2*fd) 0.01 0.05 ui ui tjref reference clock total jitter (pk-to-pk between fd/500 & 2*fd) 0.10 ui trfref reference clock rise / fall times 1.0 ns not in the pl4/spi-4-ii standards notes on reference clock timing: 1. master mode divby4 (refsel [0] = "1" & refsel[1] = ?1?). 2. the unit interval (ui) is the reciprocal of the symbol rate. 3. total jitter includes both deterministic jitter and ra ndom jitter. the random jitter is the total jitter minus the actual deterministic jitter. 4. values are measured with each pecl/lvds i nput dc coupled into a 50 ohm impedance (100 ohms differential impedance). 5. rise time is measured from the 10% threshold of the reference signal to the 90% threshold of the reference signal. 6. fall time is measured from the 90% threshold of the reference signal to the 10% threshold of the reference signal. 7. duty cycle and jitter are specified between different ial crossings of the 50% threshold of the reference signal.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 373 document no.: pmc-2001304, issue 7 18.1.4 data interface the data in table 42 and table 43 below give output and input specifications for the data and clock lanes. table 42 output data timing (rdclk, rctl, rdat) symbol parameter min typ max units comments dcoc output clock duty cycle 45 55 % fd output clock frequency 311 350 mhz max is not in the pl4/spi-4-ii standards tjoc output clock total jitter (pk-to-pk between fd/1000 & fd) 0.10 ui with max allowed jitter on pl4_refclk/tdclk djod output data deterministic jitter (pk-to-pk between fd/1000 & fd) 0.12 ui not in the pl4/spi-4-ii standards with max allowed jitter on pl4_refclk/tdclk tjod output data total jitter (pk-to-pk between fd/1000 & fd) 0.19 ui pl4/spi-4-ii standards give a max of 0.24ui with max allowed jitter on pl4_refclk/tdclk tcdsout output clock lane to any data lane skew 280 ps tdsout output differential skew 20 ps notes on output timing: 1. the unit interval (ui) is the reciprocal of the symbol rate for both clock and data. 2. total jitter includes both deterministic jitter and ra ndom jitter. the random jitter is the total jitter minus the actual deterministic jitter. 3. values are measured with each lvds output dc coupled into a 50 ohm impedance (100 ohms differential impedance). 4. jitter and skew are specified between differential crossings of the 50% thre shold of the reference signal. table 43 input data timing (tdclk, tctl, tdat) symbol parameter min typ max units comments dcic input clock duty cycle 40 60 % see note #1 fd input clock frequency 311 350 mhz djic input clock deterministic jitter (pk-to-pk between fd/1000 & 8mhz) (pk-to-pk between fd/1000 & fd) 0.01 0.10 ui ui tjic input clock total jitter (pk-to-pk between fd/1000 & fd) 0.17 ui see note #1 max not in the pl4/spi-4-ii standards djid input data deterministic jitter (pk-to-pk between fd/1000 & fd, and no jitter on pl4_refclk/tdclk) 0.36 ui see note #2 not in the pl4/spi-4-ii
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 374 document no.: pmc-2001304, issue 7 tjid input data total jitter (pk-to-pk between fd/1000 & fd, and no jitter on pl4_refclk/tdclk) 0.65 ui standards tddsin input data to data skew (any pair of data signals) 1.0 ui tdsin input differential skew 60 ps notes on input timing: 1. spec?s on tdclk (dcoc, fd, djic & tjic) on ly valid when in slave mode (refsel[0] = "0? & refsel[1] = ?0?), as tdclk is not requ ired when in either master mode. 2. when in master mode and divby4, the ?fd? in djid & tjid is twice value of the pl4_refclk frequency. when in master mode and divby2, the ?fd? in djid & tjid is the same as the pl4_refclk frequency. 3. the unit interval (ui) is the reciprocal of the symbol rate for both clock and data. 4. total jitter includes both deterministic jitter and ra ndom jitter. the random jitter is the total jitter minus the actual deterministic jitter. 5. values are measured with each lvds input dc coupled into a 50 ohm impedance (100 ohms differential impedance). 6. jitter and skew are specified between differential crossings of the 50% thre shold of the reference signal. 18.1.5 pl4 fifo status interface table 44 output status timing (tsclk, tstat[1:0]) symbol parameter min typ max units pl4_fos tsclk frequency 1/4 1/4 pl4_fin [1] pl4_dcos tsclk duty cycle 40 60 % pl4_ts_dib tstat[1:0] invalid window before rising edge of tsclk (at pm3388 pins) 1.0 ns pl4_ts_dia tstat[1:0] invalid window after rising edge of tsclk (at pm3388 pins) 2.5 ns figure 33 pl4 bus output status ac timing diagram ts-dia ts_dib ts-dia ts_dib tsclk tstat [1:0] notes on pl4 output status timing: 1. the tsclk frequency is one-quarter of the tdclk frequency. 2. assumes a load of 30 pf on t he tsclk and tstat[1:0] outputs. 3. rise time is measured from the 0.8 volt threshold of the reference signal to the 2.0 volt threshold of the reference signal.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, in c., and for its customers? internal use. 375 document no.: pmc-2001304, issue 7 4. fall time is measured from the 2.0 volt threshold of the reference signal to the 0.8 volt threshold of the reference signal. 5. duty cycle and skew are specified between crossings of the 1.4 volt threshold of the reference signal. table 45 input status timing (rsclk, rstat[1:0]) symbol parameter min typ max units pl4_fis rsclk frequency 1/4 pl4_fo ut [1] pl4_dcis rsclk duty cycle 35 65 % pl4_tsis rstat[1:0] to rising edge rsclk setup (at pm3388 pins) 2.0 ns pl4_this rstat[1:0] to rising edge rsclk hold (at pm3388 pins) 0.5 ns figure 34 pl4 bus input status ac timing diagram th ts th ts rsclk rstat [1:0] notes on pl4 input statustiming: 1. the maximum rsclk frequency shall not exceed one-quarter of the rdclk frequency. 2. rise time is measured from the 0.8 volt threshold of the reference signal to the 2.0 volt threshold of the reference signal. 3. fall time is measured from the 2.0 volt threshold of the reference signal to the 0.8 volt threshold of the reference signal. 4. duty cycle, setup and hold are specified between crossings of the 1.4 volt threshold of the reference signal. 18.1.6 pl4 fifo status interface table 46 output status timing (tsclk, tstat[1:0]) symbol parameter min typ max units pl4_fos tsclk frequency 1/4 1/4 see note #1 pl4_dcos tsclk duty cycle 40 60 % pl4_ts_dib tstat[1:0] invalid window before rising edge of tsclk (at pm3392 pins) 1.0 ns pl4_ts_dia tstat[1:0] invalid window after rising edge of tsclk (at pm3392 pins) 2.5 ns
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 376 document no.: pmc-2001304, issue 7 figure 35 pl4 bus output status ac timing diagram ts-dia ts_dib ts-dia ts_dib tsclk tstat [1:0] notes on pl4 output status timing: 1. the tsclk frequency is one-quarter of the tdclk frequency. 2. assumes a load of 30 pf on the tsclk and tstat[1:0] outputs. 3. rise time is measured from the 0.8 volt threshold of the reference signal to the 2.0 volt threshold of the reference signal. 4. fall time is measured from the 2.0 volt threshold of the reference signal to the 0.8 volt threshold of the reference signal. 5. duty cycle and skew are specified between crossings of the 1.4 volt threshold of the reference signal. table 47 input status timing (rsclk, rstat[1:0]) symbol parameter min typ max units pl4_fis rsclk frequency 1/4 see note #1 pl4_dcis rsclk duty cycle 35 65 % pl4_tsis rstat[1:0] to rising edge rsclk setup (at pm3392 pins) 2.0 ns pl4_this rstat[1:0] to rising edge rsclk hold (at pm3392 pins) 0.5 ns figure 36 pl4 bus input status ac timing diagram th ts th ts rsclk rstat [1:0] notes on pl4 input statustiming: 1. the maximum rsclk frequency shall not exceed one-quarter of the rdclk frequency. 2. rise time is measured from the 0.8 volt threshold of the reference signal to the 2.0 volt threshold of the reference signal. 3. fall time is measured from the 2.0 volt threshold of the reference signal to the 0.8 volt threshold of the reference signal. 4. duty cycle, setup and hold are specified between crossings of the 1.4 volt threshold of the reference signal.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 377 document no.: pmc-2001304, issue 7 18.2 system miscellaneous timing table 48 system miscellaneous timing symbol description min max units tvrstb rstb input pulse width 100 ns figure 37 system miscellaneous timing diagram tvrstb rstb
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 378 document no.: pmc-2001304, issue 7 18.3 xsbi interface timing table 49 xsbi interface timing symbol description min typ max units frxclk rxclk frequency (nominally 644.53125mhz) 643.5 645 mhz trxclk rxclk period (nominally 1.5515 ns) 1.550 1.56 ns twrxclk rxclk duty cycle 45 55 % trrxclk rxclk rise time (20%-80%) 100 200 300 ps tfrxclk rxclk fall time (20%-80%) 100 200 300 ps tsrxclk rxdata setup time 300 ps thrxclk rxdata hold time 300 ps ftxclk txclk frequency (nominally 644.53125mhz) 643.5 645 mhz ttxclk txclk period (nominally 1.55151 ns) 1.550 1.56 ns twtxclk txclk duty cycle 40 60 % trtxclk txclk rise time (20%-80%) 100 175 250 ps tftxclk txclk fall time (20%-80%) 100 175 250 ps tcqtxclk txdata propagation delay is measured into the recommended termination network -200 200 ps figure 38 line interface timing data valid windows data valid windows t_ txclk tc q_ ma x tc q_ min tw _tx clk tw _tx clk t_ txclk t_rxclk th_rxdata ts _ rxda ta tw_rxclk t_rxclk rxcl k+/- rxda ta+/- txc lk+/- txda ta+/-
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 379 document no.: pmc-2001304, issue 7 18.4 jtag port timing table 50 jtag port interface symbol description min max units ftck tck frequency 4 mhz thitck tck hi pulse width 100 ns tlotck tck lo pulse width 100 ns tstms tms set-up time to tck 25 ns thtms tms hold time to tck 25 ns tstdi tdi set-up time to tck 25 ns thtdi tdi hold time to tck 25 ns tptdo tck low to tdo valid 2 25 ns tvtrstb trstb pulse width 100 ns figure 39 jtag port interface timing tlotck tlotck thitck thitck tvtrstb tvtrstb tptdo thtms tstms thtdi tstdi tck tdi tms tdo trstb notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are measured with a 30 pf load on the outputs except when otherwise specified.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 380 document no.: pmc-2001304, issue 7 18.5 mdio/mdc timing table 51 mdc / mdio interface timing symbol description min typ max units tpmcd mdc period 2.4 mhz thmcd time high mdc 211 ns tlmcd time low mdc 211 ns tpmdo mdc high to valid mdio data 25 ns tsmdi mdio setup time to mdc 100 ns thmdi mdio hold time to mdc 0 ns figure 40 mdc / mdio physical timing thmdi ts m di tp md o tpmdc tl md c tl md c thmcd tpmdc thmcd mdc mdio notes on mdc/mdio i/o timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 381 document no.: pmc-2001304, issue 7 19 thermal information this product is designed to operate over a wide temperature range when used with a heat sink and is suited for outside plant equipment 1 . table 52 outside plant thermal information maximum long-term operating junction temperature (t j ) to ensure adequate long- term life. 105 c maximum junction temperature (t j ) for short-term excursions with guaranteed continued functional performance 2 . this condition will typically be reached when the local ambient temperature reaches 85 c. 125 c minimum ambient temperature (t a ) -40 c table 53 device compact model 3 junction-to-case thermal resistance, jc 0.39 c/w junction-to-board thermal resistance, jb 4.8 c/w table 54 heat sink requirements sa + cs 4 the sum of sa + cs must be less than or equal to: [(105 - t a ) / p d ] - jc ] c/w where: t a is the ambient temperature at the heat sink location p d is the operating power dissipated in the package sa and cs are required for long-term operation jb jc board device compact model cs sa junction case heat sink ambient power depends upon the operating mode. to obtai n power information, refer to ?high? power values in section section 18.1 power requirements. notes 1. the minimum ambient temperature requirement for outside plant equipment meets the minimum ambient temperature requirement for industrial equipment 2. short-term is used as defined in telcordia te chnologies generic requirements gr-63-core core 3. jc , the junction-to-case thermal resistance, is a measured nominal value plus two sigma. jb , the junction-to-board thermal resistance, is obtained by simulating conditions described in jedec standard jesd 51-8; for more information about this standard, 4. sa is the thermal resistance of the heat sink to ambient. cs is the thermal resistance of the heat sink attached material. the maximum sa required for the airspeed at the location of the device in the system with all components in place
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 382 document no.: pmc-2001304, issue 7 19.1 power requirements table 55 power consumption mode parameter typ high max units master by 2 iddop (vddi) 2.583 3.43 3.544 a iddop (vddo) 0.465 0.43 0.467 a iddop (avdl) 0.078 0.10 0.104 a iddop (avdh) 0.043 0.06 0.066 a total power 6.469 8.36 - w master by 4 iddop (vddi) 2.583 3.48 3.597 a iddop (vddo) 0.465 0.43 0.467 a iddop (avdl) 0.078 0.10 0.105 a iddop (avdh) 0.043 0.06 0.067 a total power 6.469 8.47 - w slave- immediate iddop (vddi) 2.583 3.43 3.544 a iddop (vddo) 0.465 0.43 0.467 a iddop (avdl) 0.078 0.10 0.104 a iddop (avdh) 0.043 0.06 0.066 a total power 6.469 8.36 - w slave-deferred iddop (vddi) 2.583 3.43 3.544 a iddop (vddo) 0.465 0.43 0.467 a iddop (avdl) 0.078 0.10 0.104 a iddop (avdh) 0.043 0.06 0.066 a total power 6.469 8.36 - w notes: 1. typical idd values are calculated as the mean value of current under the following conditions: typically processed silicon, nominal supply voltag e, tj=60 c, outputs loaded with 30 pf, and a normal amount of traffic or signal activity. these values are suitable for evaluating typical device performance in a system. 2. max idd values are currents guaranteed by the pr oduction test program, product validation results and/or characterization over process for operatin g currents at the maximum operating voltage and operating temperature that yields the highest current (including outputs loaded to 30pf). 3. typical power values are calculated using the formula: power = i(vddnomi x iddtypi) where i denotes all the various power supplies on the device, vddnomi is the nominal voltage for supply i, and iddtypi is the typical current for supp ly i (as defined in note 1 above). these values are suitable for evaluating typical device performance in a system.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 383 document no.: pmc-2001304, issue 7 4. high power values are a ?normal high power? estimate, calculated using the formula: power = i(vddmaxi x iddhighi) where i denotes all the various power supplies on the device, vddmaxi is the maximum operating voltage for supply i, and iddhighi is the current for supply i. iddhigh values are calculated as the mean value plus two sigmas (2 ) of measured current under the following conditions: tj=105 c, outputs loaded with 30 pf. these values are suitable for evaluating board and device thermal characteristics.
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 384 document no.: pmc-2001304, issue 7 20 mechanical information figure 41 896 pin fcbga -31x31 mm body - (3m substrate) e d1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 a1 ball corner a b c d e f g h j k l m n p r t u v w y aa ab e b ac ad ae af ag ah aj ak e1 6. m m c c a b a a1 seating plane a3 a2 a1 ball pad corner a1 ball indicator c 2x d a e b c 2x notes: 1) all dimensions in millimeter. 2) dimension aaa denotes package body profile. 3) dimension bbb denotes parallel. 4) dimension ccc denotes flatness. 5) dimension ddd denotes coplanarity. 6) diameter of solder mask opening is 0.530mm (smd).
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 385 document no.: pmc-2001304, issue 7 figure 42 896 pin fcbga -31x31 mm body - (hdbu substrate) e d1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 a1 ball corner a b c d e f g h j k l m n p r t u v w y aa ab e b ac ad ae af ag ah aj ak e1 5. m m c c a b a a1 seating plane a2 a1 ball pad corner a1 ball indicator c 2x d a e b c 2x notes: 1) all dimensions in millimeter. 2) dimension aaa denotes package body profile. 3) dimension bbb denotes parallel. 4) dimension ddd denotes coplanarity. 5) diameter of solder mask opening is 0.530mm (smd). 6) package compliant to jedec registered outline ms-034, variation aan-1 .
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 386 document no.: pmc-2001304, issue 7 21 ordering information table 56 ordering information part no. description pm3392-fi s/uni-1x10ge 896-pin fcbga (3m substrate) pm3392h-fi s/uni-1x10ge 896-pin fcbga (hdbu substrate ) PM3392-FGI s/uni-1x10ge 896-pin fcbga (hdbu substrate, rohs-compliant)
downloaded by ihs parts management inc. of ihs inc on sunday, 16 september, 2007 10:18:06 pm s/uni-1x10ge assp telecom standard product data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. 387 document no.: pmc-2001304, issue 7 notes

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